IP Library Granted Patent US 7,924,047
Granted Patent B2
US 7,924,047 · App. 12/073,755 · Granted Apr 12, 2011

Semiconductor apparatus

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Quick Facts
Patent No.
US 7,924,047
App. No.
12/073,755
Granted
Apr 12, 2011
Kind
B2
Abstract

The on-die termination circuit of the present invention includes a main resistance circuit and an adjustment circuit. The main resistance circuit is provided with a resistance element and a transistor that is turned OFF when the on-die termination circuit is to be placed in the OFF state and turned ON when the on-die termination circuit is to be placed in the ON state. The adjustment circuit is provided with transistors that are both connected together in parallel and connected in parallel to the main resistance circuit, and that are turned ON or OFF when the on-die termination circuit is placed in the ON state so as to adjust the termination resistance of the entire on-die termination circuit.

Claims (35)

1. A semiconductor apparatus including an on-die termination circuit, the on-die termination circuit comprising:

a main resistance circuit that is provided with one or more resistance elements and one or more transistors that are turned OFF when the on-die termination circuit is to be placed in the OFF state and turned ON when the on-die termination circuit is to be placed in the ON state; and

an adjustment circuit that is provided with a plurality of transistors that are connected in parallel to each other and further connected in parallel to said main resistance circuit, said plurality of transistors being turned ON or OFF when said on-die termination circuit is placed in the ON state so as to adjust the termination resistance of the entirety of the on-die termination circuit,

wherein the adjustment circuit does not contain resistance elements.

2. The semiconductor apparatus according to claim 1 , wherein the resistance of transistors that make up said adjustment circuit is at least 2.5 times the target value of the termination resistance.

3. The semiconductor apparatus according to claim 1 , wherein transistors that make up said main resistance circuit and said adjustment circuit are NMOS transistors, PMOS transistors, or CMOS transistors with which NMOS transistors and PMOS transistors are associated.

4. The semiconductor apparatus according to claim 1 , wherein transistors of the main resistance circuit and the adjustment circuit are controlled in response to a control signal.

5. The semiconductor apparatus according to claim 1 , wherein a termination voltage is a power supply voltage and wherein the termination voltage is connected to source terminals of the one or more transistors of the main resistance circuit and source terminals of the plurality of transistors of the adjustment circuit.

6. The semiconductor apparatus according to claim 1 , wherein a termination voltage is a ground voltage and wherein the termination voltage is connected to source terminals of the one or more transistors of the main resistance circuit and source terminals of the plurality of transistors of the adjustment circuit.

7. A semiconductor apparatus including an on-die termination circuit, the on-die termination circuit comprising:

a main resistance circuit that is provided with one or more resistance elements and one or more transistors that are turned OFF when the on-die termination circuit is to be placed in the OFF state and turned ON when the on-die termination circuit is to be placed in the ON state; and

an adjustment circuit that is provided with one or more transistors that are both connected together in parallel and connected in parallel to said main resistance circuit, said transistors being turned ON or OFF when said on-die termination circuit is placed in the ON state so as to adjust the termination resistance of the entirety of the on-die termination circuit;

wherein the adjustment circuit does not contain resistance elements;

wherein a termination voltage, which is a power supply voltage, is connected to source terminals of a first portion of the one or more transistors of the main resistance circuit and source terminals of a first portion of the one or more transistors of the adjustment circuit;

wherein a termination voltage, which is ground, is connected to source terminals of a second portion of the one or more transistors of the main resistance circuit and source terminals of a second portion of the one or more transistors of the adjustment circuit; and

wherein the first portion of the one or more transistors of the main resistance circuit and the first portion of the one or more transistors of the adjustment circuit share a terminal pin with the second portion of the one or more transistors of the main resistance circuit and the second portion of the one or more transistors of the adjustment circuit such that the termination voltage is set to one half the power supply voltage.

8. A semiconductor apparatus including an on-die termination circuit, the on-die termination circuit comprising:

a main resistance circuit that is provided with one or more resistance elements and one or more transistors that are controlled in response to a control signal; and

an adjustment circuit that is provided with a plurality of electrical paths that are connected in parallel to each other and further connected in parallel to the main resistance circuit, each of the electrical paths comprising a transistor, the transistor in each of the electrical paths except for at least one thereof being turned ON and the transistor in each of remaining one or ones of the electrical paths being turn OFF,

wherein the adjustment circuit does not contain resistance elements.

9. The semiconductor apparatus according to claim 8 , wherein the resistance of transistors that make up said adjustment circuit is at least 2.5 times the target value of the termination resistance.

10. The semiconductor apparatus according to claim 8 , wherein transistors that make up said main resistance circuit and said adjustment circuit are NMOS transistors, PMOS transistors, or CMOS transistors with which NMOS transistors and PMOS transistors are associated.

11. The semiconductor apparatus according to claim 8 , wherein a termination voltage is a power supply voltage and wherein the termination voltage is connected to source terminals of the one or more transistors of the main resistance circuit and a source terminal of the transistor of each of the electrical paths of the adjustment circuit.

12. The semiconductor apparatus according to claim 8 , wherein a termination voltage is a ground voltage and wherein the termination voltage is connected to source terminals of the one or more transistors of the main resistance circuit and a source terminal of the transistor of each of the electrical paths of the adjustment circuit.

13. A semiconductor apparatus including an on-die termination circuit, the on-die termination circuit comprising:

a main resistance circuit that is provided with one or more resistance elements and one or more transistors that are controlled in response to a control signal; and

an adjustment circuit that is provided with one or more transistors that are both connected together in parallel and connected in parallel to said main resistance circuit, said transistors being controlled in response to said control signal;

wherein the adjustment circuit does not contain resistance elements;

wherein a termination voltage which is a power supply voltage, is connected to source terminals of a first portion of the one or more transistors of the main resistance circuit and source terminals of a first portion of the one or more transistors of the adjustment circuit;

wherein a termination voltage which is ground, is connected to source terminals of a second portion of the one or more transistors of the main resistance circuit and source terminals of a second portion of the one or more transistors of the adjustment circuit; and

wherein the first portion of the one or more transistors of the main resistance circuit and the first portion of the one or more transistors of the adjustment circuit share a terminal pin with the second portion of the one or more transistors of the main resistance circuit and the second portion of the one or more transistors of the adjustment circuit such that the termination voltage is set to one half the power supply voltage.

14. The semiconductor apparatus according to claim 7 , wherein the resistance of transistors that make up said adjustment circuit is at least 2.5 times the target value of the termination resistance.

15. The semiconductor apparatus according to claim 7 , wherein transistors that make up said main resistance circuit and said adjustment circuit are NMOS transistors, PMOS transistors, or CMOS transistors with which NMOS transistors and PMOS transistors are associated.

16. The semiconductor apparatus according to claim 13 , wherein the resistance of transistors that make up said adjustment circuit is at least 2.5 times the target value of the termination resistance.

17. The semiconductor apparatus according to claim 13 , wherein transistors that make up said main resistance circuit and said adjustment circuit are NMOS transistors, PMOS transistors, or CMOS transistors with which NMOS transistors and PMOS transistors are associated.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2018
From: LONGITUDE SEMICONDUCTOR S.A.R.L.
To: LONGITUDE LICENSING LIMITED
Reel/Frame 046867/0248 →
CHANGE OF NAME Recorded Aug 24, 2016
From: PS5 LUXCO S.A.R.L.
To: LONGITUDE SEMICONDUCTOR S.A.R.L.
Reel/Frame 039793/0880 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2016
From: PS4 LUXCO S.A.R.L.
To: PS5 LUXCO S.A.R.L.
Reel/Frame 039818/0506 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2014
From: ELPIDA MEMORY, INC.
To: PS4 LUXCO S.A.R.L.
Reel/Frame 032899/0588 →
SECURITY AGREEMENT Recorded Jul 29, 2013
From: PS4 LUXCO S.A.R.L.
To: ELPIDA MEMORY INC.
Reel/Frame 032414/0261 →