Semiconductor device including mounting board with stitches and first and second semiconductor chips
View Patent ↗A first memory chip ( 103 a ) and a second memory chip ( 103 b ) mounted in this order on one surface of a mounting board ( 101 ) each have a rectangular planar shape and include a plurality of electrode pads formed in a single line along one side of the rectangle. An electrode pad line of the second memory chip ( 103 b ) is formed in parallel with an electrode pad line of the first memory chip ( 103 a ). A chip select pad is disposed on an end of the electrode pad line. Control pads, address pads, or data pads ( 113 a ) of the first memory chip ( 103 a ) are wire bonded to first stitches ( 109 ) formed in a single line along one side of the rectangle. A chip select pad ( 121 a ) and a chip select pad ( 121 b ) are wire bonded to second stitches ( 111 ) formed in a line along a side adjacent to a side of the chip select pad ( 121 a ). Accordingly, an increase in package area is suppressed when a plurality of memory chips are stacked.
1. A semiconductor device, comprising:
a mounting board comprising first stitches arranged along a first line on a surface thereof, and comprising-second stitches arranged along a second line on the surface thereof, the first line and the second line intersecting with each other;
a first semiconductor chip mounted on the mounting board and comprising first electrode pads arranged along one side of the first semiconductor chip, the one side being substantially in parallel with the first stitches; and
a second semiconductor chip mounted on the first semiconductor chip and comprising second electrode pads arranged along one side of the second semiconductor chip, the one side of the second semiconductor chip being substantially in parallel with the first electrode pads,
wherein one of the second stitches is connected to one of the first electrode pads which is adjacent to the one of the second stitches through a wire, whereas the one of the second stitches is unconnected to other first electrode pads and respective second electrode pads through a wire.
2. The semiconductor device according to claim 1 , wherein another one of the second stitches is connected to one of the second electrode pads which is adjacent to the another one of the second stitches through a wire, whereas the another one of the second stitches is unconnected to other second electrode pads and respective first electrode pads.
3. The semiconductor device according to claim 2 , wherein the other first electrode pads are connected to the first stitches and the other second electrode pads through wires.
4. The semiconductor device according to claim 3 , further comprising a third semiconductor chip mounted on the second semiconductor chip and comprising third electrode pads arranged along one side of the third semiconductor chip, the one side of the third semiconductor chip being substantially in parallel with the second electrode pads, and
wherein a further one of the second stitches is connected to one of the third electrode pads which is adjacent to the further one of the second stitches through a wire, whereas the further one of the second stitches is unconnected to other third electrode pads and the respective second electrode pads.
5. The semiconductor device according to claim 4 , wherein the one of the second stitches is unconnected to respective third electrode pads through a wire,
wherein the another one of the second stitches is unconnected to the respective third electrode pads through a wire, and
wherein the further one of the second stitches is unconnected to the respective first electrode pads through a wire.
6. The semiconductor device according to claim 1 , wherein a chip select signal for the first semiconductor chip is input into the one of the second stitches.
7. The semiconductor device according to claim 1 , wherein the first and second semiconductor chips comprise memory chips.
8. The semiconductor device according to claim 1 , wherein an area of the first semiconductor chip on which the first electrode pads are formed is larger than an area of the second semiconductor chip on which the second electrode pads are formed.
9. The semiconductor device according to claim 4 , wherein the third semiconductor chip is positioned immediately above the first semiconductor chip.
10. The semiconductor device according to claim 1 , wherein the first line is perpendicular to the second line.
11. The semiconductor device according to claim 1 , wherein the one of the second stitches is connected to one of the first electrode pads which is most adjacent to the one of the second stitches among the first electrode pads through a wire.
12. The semiconductor device according to claim 1 , wherein the first semiconductor chip comprises a memory chip.
13. The semiconductor device according to claim 1 , wherein the second semiconductor chip comprises a memory chip.
14. A semiconductor device, comprising:
a mounting board comprising a plurality of first stitches arranged along a first line on a surface thereof, and comprising a plurality of second stitches arranged along a second line on the surface thereof, the first line and the second line intersecting with each other;
a first semiconductor chip mounted on the mounting board and comprising a plurality of first electrode pads arranged along a first side of the first semiconductor chip, the first side being substantially parallel with the plurality of first stitches; and
a second semiconductor chip mounted on the first semiconductor chip and comprising a plurality of second electrode pads arranged along a first side of the second semiconductor chip, the first side of the second semiconductor chip being substantially parallel with the first electrode pads,
wherein a first one of the plurality of second stitches is connected to a first one of the first electrode pads, the first of the first electrode pads being adjacent to the first one of the second stitches, and is connected thereto via a wire, and
wherein the plurality of the first stitches are electrically connected to respective adjacent ones of the plurality of the first electrode pads, other than the first one of the plurality of first electrode pads, and respective adjacent ones of the plurality of the second electrode pads, other than the first one of the plurality of second electrode pads.
15. The semiconductor device according to claim 14 , wherein a second one of the plurality of second stitches is connected to a first one of the second electrode pads, the first of the second electrode pads being adjacent to the first one of the second stitches, and is connected thereto via a wire.
16. The semiconductor device according to claim 14 , further comprising a third semiconductor chip mounted on the second semiconductor chip and comprising a plurality of third electrode pads arranged along a first side of the third semiconductor chip, the first side being substantially parallel with the second electrode pads,
wherein a third one of the second stitches is electrically connected to a respective adjacent first one of the third electrode pads through a wire, and
wherein the plurality of the first stitches are electrically connected to respective adjacent ones of the plurality of the third electrode pads, other than the first one of the plurality of third electrode pads.