Clock and data recovery circuit
View Patent ↗The phase detector compares the phases of a synchronous clock signal and serial data and outputs a phase error signal corresponding to a comparison result. The second integrator performs integration of the phase error signal to obtain a phase correction control signal for tracking phase shift of the serial data. The first integrator performs integration of the phase error signal in each smoothing period with a predetermined length to obtain a smoothed error signal. The pattern generator generates a pattern for changing the phase of the synchronous clock signal at a frequency corresponding to the smoothed error signal in each pattern generation period with a predetermined length and outputs the pattern as a frequency correction control signal. The first integrator receives the frequency correction control signal which is fed back and changes the length of the smoothing period according to the direction of a change in the frequency of generating the frequency correction control signal.
1. A clock and data recovery circuit comprising:
a clock generator to generate a synchronous clock signal;
a phase detector to compare a phase of the synchronous clock signal obtained by the clock generator with a phase of serial data and obtain a phase error signal corresponding to a comparison result of the comparing;
a phase tracking loop to acquire a phase correction control signal for tracking phase shift of the serial data based on the phase error signal; and
a frequency tracking loop to acquire a frequency correction control signal for tracking frequency shift of the serial data based on the phase error signal, wherein
the clock generator corrects the phase of the synchronous clock signal based on the frequency correction control signal and the phase correction control signal,
the frequency tracking loop includes:
a first smoothing unit to receive the phase error signal obtained by the phase detector as an input signal, smooth the input signal in each smoothing period with a predetermined length and output a smoothed error signal; and
a pattern generator to generate a pattern for changing the phase of the synchronous clock signal at a frequency corresponding to the smoothed error signal in each pattern generation period with a second predetermined length and output the pattern as the frequency correction control signal, and
the first smoothing unit changes the length of the smoothing period according to a direction of a change in the frequency of the frequency correction control signal.
2. The clock and data recovery circuit according to claim 1 , wherein
the pattern generator generates the pattern at substantially equal intervals in each pattern generation period.
3. The clock and data recovery circuit according to claim 2 , wherein
the first smoothing unit sets the length of the smoothing period to be shorter when the frequency of the frequency correction control signal is decreasing than when the frequency is increasing.
4. The clock and data recovery circuit according to claim 3 , wherein
the frequency tracking loop further includes a second smoothing unit connected between the phase detector and the first smoothing unit, to smooth the phase error signal obtained by the phase detector, and
the first smoothing unit receives the phase error signal smoothed by the second smoothing unit as an input signal.
5. The clock and data recovery circuit according to claim 4 , wherein
the phase tracking loop acquires the phase error signal smoothed by the second smoothing unit as the phase correction control signal.
6. The clock and data recovery circuit according to claim 2 , wherein
the frequency tracking loop further includes a second smoothing unit connected between the phase detector and the first smoothing unit, to smooth the phase error signal obtained by the phase detector, and
the first smoothing unit receives the phase error signal smoothed by the second smoothing unit as an input signal.
7. The clock and data recovery circuit according to claim 6 , wherein
the phase tracking loop acquires the phase error signal smoothed by the second smoothing unit as the phase correction control signal.
8. The clock and data recovery circuit according to claim 1 , wherein
the first smoothing unit sets the length of the smoothing period to be shorter when the frequency of the frequency correction control signal is decreasing than when the frequency is increasing.
9. The clock and data recovery circuit according to claim 8 , wherein
the frequency tracking loop further includes a second smoothing unit connected between the phase detector and the first smoothing unit, to smooth the phase error signal obtained by the phase detector, and
the first smoothing unit receives the phase error signal smoothed by the second smoothing unit as an input signal.
10. The clock and data recovery circuit according to claim 9 , wherein
the phase tracking loop acquires the phase error signal smoothed by the second smoothing unit as the phase correction control signal.
11. The clock and data recovery circuit according to claim 1 , wherein
the first smoothing unit comprises a first integrator, and
the pattern generator has a pattern length corresponding to the pattern generation period with the second predetermined length, counts an integral of the first integrator, and generates the frequency correction control signal based on a count result.
12. The clock and data recovery circuit according to claim 11 , wherein
the input signal of the first integrator includes a carry signal indicating a need for shifting the phase of the synchronous clock signal and a sign signal indicating a direction of shifting the phase of the synchronous clock signal.
13. The clock and data recovery circuit according to claim 12 , wherein
the first integrator comprises an up/down counter to count up or count down according to the input signal, and
the first integrator sets a count width to be smaller when the frequency of the frequency correction control signal is decreasing than when the frequency is increasing.
14. The clock and data recovery circuit according to claim 11 , wherein
the input signal of the first integrator includes an up signal indicating that the phase of the synchronous clock signal is leading and a down signal indicating that the phase of the synchronous clock signal delays.
15. The clock and data recovery circuit according to claim 14 , wherein
the first integrator comprises an up/down counter to count up or count down according to the input signal, and
the first integrator sets a count width to be smaller when the frequency of the frequency correction control signal is decreasing than when the frequency is increasing.
16. The clock and data recovery circuit according to claim 11 , wherein
the frequency tracking loop further includes a second smoothing unit connected between the phase detector and the first smoothing unit, to smooth the phase error signal obtained by the phase detector, and
the first smoothing unit receives the phase error signal smoothed by the second smoothing unit as an input signal.
17. The clock and data recovery circuit according to claim 16 , wherein
the phase tracking loop acquires the phase error signal smoothed by the second smoothing unit as the phase correction control signal.
18. The clock and data recovery circuit according to claim 1 , wherein
the frequency tracking loop further includes a second smoothing unit connected between the phase detector and the first smoothing unit, to smooth the phase error signal obtained by the phase detector, and
the first smoothing unit receives the phase error signal smoothed by the second smoothing unit as an input signal.
19. The clock and data recovery circuit according to claim 18 , wherein
the phase tracking loop acquires the phase error signal smoothed by the second smoothing unit as the phase correction control signal.