Semiconductor integrated circuit and method of testing same
View Patent ↗A semiconductor integrated circuit includes S PLLs (S is an integer satisfying S≧2), and the (k−1)th PLL 12 (k-1) (k is an integer satisfying 2≦k≦S) is connected to the kth PLL 12 k in the test mode. In this manner, the examination of S PLLs can be performed in a single test, and thereby it can reduce the time needed to examine PLLs in the semiconductor integrated circuit having a plurality of PLLs.
1. A semiconductor integrated circuit comprising:
S phase-locked loop circuits (S is an integer satisfying S≧2), the (k−1)th phase-locked loop circuit of the S phase-locked loop circuits being connected to the kth phase-locked loop circuit in series (k is an integer satisfying 2≦k≦S) in a test mode; and
a circuit connected between the (k−1)th phase-locked loop circuit and the kth phase-locked loop circuit in the test mode, and one of frequency-dividing and frequency-multiplying an output clock from the (k−1)th phase-locked loop circuit such that a frequency of a clock inputted to the kth phase-locked loop circuit in a normal mode is the same as a frequency of a clock inputted to the kth phase-locked loop circuit in the test mode.
2. The semiconductor integrated circuit of claim 1 , wherein the (k−1)th phase-locked loop circuit and the kth phase-locked loop circuit are connected such that clocks having the same frequencies as in the normal mode are inputted to the (k−1)th phase-locked loop circuit and the kth phase-locked loop circuit in the test mode.
3. The semiconductor integrated circuit of claim 1 , wherein the circuit comprises a frequency dividing circuit connected between the (k−1)th phase-locked loop circuit and the kth phase-locked loop circuit in the test mode, and
wherein the frequency dividing circuit frequency-divides the output clock from the (k−1)th phase-locked loop circuit such that a clock having the same frequency as in the normal mode is inputted to the kth phase-locked loop circuit in the test mode.
4. The semiconductor integrated circuit of claim 2 , wherein the circuit comprises a frequency dividing circuit connected between the (k−1)th phase-locked loop circuit and the kth phase-locked loop circuit in the test mode,
wherein the frequency dividing circuit frequency-divides the output clock from the (k−1)th phase-locked loop circuit such that a clock having the same frequency as in the normal mode is inputted to the kth phase-locked loop circuit in the test mode.
5. The semiconductor integrated circuit of claim 3 , wherein the frequency dividing circuit has a frequency division factor equivalent to the reciprocal of the frequency multiplication factor of the (k−1)th phase-locked loop circuit.
6. The semiconductor integrated circuit of claim 1 , wherein the circuit comprises a frequency dividing circuit connected between the (k−1)th phase-locked loop circuit and said kth phase-locked loop circuit in the test mode, and
wherein a clock having the same frequency as in the normal mode is inputted to the kth phase-locked loop circuit in the test mode, and the frequency dividing circuit has a variable frequency division factor.
7. The semiconductor integrated circuit of claim 1 , wherein the circuit comprises a phase-locked loop circuit designed for connection connected between the (k−1)th phase-locked loop circuit and the kth phase-locked loop circuit in the test mode,
wherein the phase-locked loop circuit designed for connection frequency-multiplies the output clock from the (k−1)th phase-locked loop circuit such that a clock having the same frequency as in the normal mode is inputted to the kth phase-locked loop circuit in the test mode.
8. The semiconductor integrated circuit of claim 2 , wherein the circuit comprises a phase-locked loop circuit designed for connection connected between the (k−1)th phase-locked loop circuit and the kth phase-locked loop circuit in the test mode, and
wherein the phase-locked loop circuit designed for connection frequency-multiplies the output clock from the (k−1)th phase-locked loop circuit such that a clock having the same frequency as in the normal mode is inputted to the kth phase-locked loop circuit in the test mode.
9. The semiconductor integrated circuit of claim 1 , wherein the clock inputted to the kth phase-locked loop circuit in a normal mode comprises a clock generated by an oscillator clock and the clock inputted to the kth phase-locked loop circuit in the test mode comprises an output clock from the circuit.
10. The semiconductor integrated circuit of claim 9 , further comprising:
a first selector which is connected to the kth phase-locked loop circuit and selects and outputs the clock generated by an oscillator clock to the kth phase-locked loop circuit in a normal mode and selects and outputs the output clock from the circuit to the kth phase-locked loop circuit in a test mode.
11. The semiconductor integrated circuit of claim 10 , further comprising:
a second selector which is connected to the (k−1)th phase-locked loop circuit and selects and outputs the clock generated by an oscillator clock to the (k−1)th phase-locked loop circuit in a normal mode and selects and outputs a test clock generated by a signal generator of a test device to the (k−1)th phase-locked loop circuit in a test mode.
12. The semiconductor integrated circuit of claim 11 , further comprising:
a first logic circuit, a clock inputted to the first logic circuit in a test mode comprising the test clock frequency multiplied at the (k−1)th phase-locked loop circuit; and
a second logic circuit, a clock inputted to the second logic circuit in a test mode comprising the test clock frequency multiplied at the kth phase-locked loop circuit.
13. The semiconductor integrated circuit of claim 11 , wherein the first and second selectors are controlled by a control signal of the test device.
14. A semiconductor integrated circuit comprising:
P phase-locked loop circuit groups (P is an integer satisfying P≧2), each of the phase-locked loop circuit group having S phase-locked loop circuits (S is an integer satisfying S≧2) to which clocks having the same frequency is inputted in a normal mode;
a first frequency dividing circuit connected in series between the (k−1)th phase-locked loop circuit (k is an integer satisfying 2≦k≦S) and the kth phase-locked loop circuit of the P phase-locked loop circuit groups in a test mode; and
a second frequency dividing circuit connected between the (r−1)th phase-locked loop circuit group (r is an integer satisfying 2≦r≦P) and the rth phase-locked loop circuit group in the test mode,
wherein the (k−1) phase-locked loop circuit and the kth phase-locked loop circuit are connected in series, and the (r−1)th phase-locked loop circuit group and the rth phase-locked loop circuit group are connected in series,
wherein the first frequency dividing circuit frequency-divides the output clock from the (k−1)th phase-locked loop circuit such that the resulting frequency is equal to the frequency of an input clock to the kth phase-locked loop circuit operating in the normal mode, and
wherein the second frequency dividing circuit frequency-divides the output clock from the Sth phase-locked loop circuit of the (r−1)th phase-locked loop circuit group such that the resulting frequency is equal to the frequency of an input clock to the first phase-locked loop circuit of the rth phase-locked loop circuit group operating in the normal mode.
15. The semiconductor integrated circuit of claim 14 , wherein the P phase-locked loop circuit groups comprise:
a first phase-locked loop circuit group and a third phase-locked loop circuit group, to both of which clocks having the same frequency are inputted in the normal mode, an output clock from the first phase-locked loop circuit group being inputted to a third frequency dividing circuit in the normal mode and the test mode; and
a second phase-locked loop circuit group connected to the first phase-locked loop circuit group through the third frequency dividing circuit, the output clock from the third frequency dividing circuit being inputted to the second phase-locked loop circuit group in the normal mode and test mode,
wherein the third frequency dividing circuit connects the second phase-locked loop circuit group to the third phase-locked loop circuit group.
16. A method of testing a semiconductor integrated circuit comprising S phase-locked loop circuits (S is an integer satisfying S≧2), wherein the (k−1)th phase-locked loop circuit (k is an integer satisfying 2≦k≦S) is connected to the kth phase-locked loop circuit in series, the method comprising:
inputting a test signal to the phase-locked loop circuit in the most upstream of the semiconductor integrated circuit;
examining an output clock from a phase-locked loop circuit of the phase-locked loop circuits in the most downstream of the semiconductor integrated circuit; and
one of frequency-dividing and frequency-multiplying an output clock from the (k−1)th phase-locked loop circuit such that a frequency of a clock inputted to the kth phase-locked loop circuit in a normal mode is the same as a frequency of a clock inputted to the kth phase-locked loop circuit in the test mode.