Rd algorithm improvement for NROM technology

1. A method of selecting a read voltage level for reading a non-volatile memory (NVM) cell comprising:

using an initial value for the read voltage, and performing a read operation;

comparing an actual number of bits found to an expected number of bits;

if there is a discrepancy between the actual number and the expected number, adjusting the read voltage level, based on variable data, and

wherein the variable data is selected from the group consisting of statistics available, level occupation, neighbor level, previous chunks data, and other data used during read, program or erase.

2. The method of claim 1 , wherein the NVM cell is a floating gate memory cell.

3. The method of claim 1 , wherein the NVM cell is an NROM memory cell.

4. The method of claim 1 , wherein:

the read voltage level is adjusted based on a number of missing bits.

5. The method of claim 4 , wherein:

if many bits are missing, making a larger adjustment than if only a few bits are missing.

6. The method of claim 1 , further comprising:

basing the adjustment upon a result of a previous read operation.

7. The method of claim 1 , further comprising:

basing the initial value upon a result of a previous read operation.

8. The method of claim 1 , further comprising:

basing the adjustment at a selected program level based upon a result obtained at another program level.

9. The method of claim 1 , further comprising:

basing the adjustment upon how many times the memory cell has been cycled.

10. The method of claim 1 , further comprising:

basing the adjustment upon an operating temperature of the memory cell.

11. The method of claim 1 , further comprising:

basing the adjustment upon evidence accumulated during testing or simulation of the memory cell.

12. The method of claim 1 , wherein a plurality of memory cells are programmed at a plurality of program levels, further comprising:

basing the adjustment upon how many memory cells are at each program level.

13. The method of claim 1 , further comprising:

basing the adjustment upon statistical algorithm concepts.

14. The method of claim 1 , wherein a plurality of memory cells are programmed at a plurality of program levels, further comprising:

basing the adjustment upon at least one of a total number of bits per level, a total number of errors per level, and sigma.

15. The method of claim 1 , wherein a plurality of memory cells are programmed at a plurality of program levels, further comprising:

basing the adjustment upon at least one of accumulated knowledge of statistics over chunks, accumulated knowledge of statistics on the same chunk, and neighbor level information.

16. The method of claim 1 , further comprising:

making the adjustment based upon shift values (deltas) in a lookup table.

17. The method of claim 16 , wherein a plurality of memory cells are programmed at a plurality of program levels, further comprising:

a lookup table for each program level.

18. The method of claim 16 , wherein:

the lookup table is resident in reference cells.

19. The method of claim 1 , further comprising:

after adjusting the read voltage level, using the adjusted read voltage level and performing another read operation;

making a further comparison of an actual number of bits found to the expected number of bits; and

if there is a discrepancy between the actual number and the expected number, further adjusting the read voltage level using a different technique than was used in the first adjustment.

20. The method of claim 19 , wherein:

the different technique comprises moving the read voltage level by a fixed amount.

21. The method of claim 1 , further comprising:

after adjusting the read voltage level, using the adjusted read voltage level and performing another read operation;

making a further comparison of an actual number of bits found to the expected number of bits; and

if there is a discrepancy between the actual number and the expected number, further adjusting the read voltage level using a same technique as was used in the first adjustment.

22. The method of claim 21 , wherein:

the same technique comprises using a lookup table.

23. The method of claim 1 , further comprising:

after adjusting the read voltage level, using the adjusted read voltage level and performing another read operation;

making a further comparison of an actual number of bits found to the expected number of bits; and

if there is a discrepancy between the actual number and the expected number, further adjusting the read voltage level using a similar technique as was used in the first adjustment.

24. The method of claim 23 , wherein:

the similar technique comprises using a different lookup table.

25. The method of claim 1 , wherein:

a subsequent chunk of memory is read and the read voltage is adjusted based on results of determining a delta for adjusting read voltage in a previously read chunk of memory.

26. The method of claim 1 , further comprising:

basing the adjustment at a selected program level based upon a number of bits at other program levels.

27. The method of claim 1 , further comprising:

basing the adjustment at a selected program level in a selected chunk of memory based upon a number of bits at the same level in other chunks of memory.

28. The method of claim 27 , further comprising:

giving more weight to the bits in the selected chunk.

29. The method of claim 1 , further comprising:

basing the adjustment at a selected program level in a selected chunk of memory based upon a number of bits at another program level in the selected chunk of memory, if there are more than a predefined number of bits in the other program level.

30. The method of claim 1 , further comprising:

continuing to adjust the read voltage level until the discrepancy between the actual number and the expected number is minimized.

31. The method of claim 30 , further comprising:

implementing stopping conditions if it is not possible to assess if a bit is a part of a distribution at a given program level or is a fluctuating bit.