Fine-pitch routing in a lead frame based system-in-package (SIP) device
View Patent ↗In an example embodiment, there is a package substrate ( 200 ) for mounting an integrated circuit (IC) device ( 205 ). The package substrate comprises an IC device placement area ( 290 ) surrounded by pad landings ( 215 ). For placing surface mount devices in vicinity of the pad landings, there is a plurality of component pads ( 235 a, 235 b, 235 c, 235 d ). The plurality of component pads surrounds the pad landings ( 215 ). A plurality of device pins ( 225 a, 225 b, 225 c, 225 d, 245 a, 245 b, 245 c, 245 d ) surrounds the component pads. One or more of the plurality of device pins, having fine-pitch conductive paths ( 270 ), couple the one or more of the plurality of device pins to a set of corresponding pad landings ( 215 ) or to a set of corresponding component pads; the fine-pitch conductive paths ( 270 ) traverse regions between the plurality of component pads.
1. A package substrate for mounting an integrated circuit device, the package substrate comprising:
an IC device placement area surrounded by pad landings;
a plurality of component pads for placing surface mount devices in vicinity of the pad landings, the plurality of component pads surrounding the pad landings;
and a plurality of device pins surrounding the component pads, one or more of the plurality of device pins having fine-pitch conductive paths coupling the one or more of the plurality of device pins to a set of corresponding pad landings or to a set of corresponding component pads, the fine-pitch conductive paths traversing regions between the plurality of component pads; and
wherein the fine pitch conductive paths are routed at less than about 80 μm in terms of cumulative line width and spacing.
2. A package substrate for mounting an integrated circuit device, the package substrate comprising:
an IC device placement area surrounded by pad landings;
a plurality of component pads for placing surface mount devices in vicinity of the pad landings, the plurality of component pads surrounding the pad landings;
and a plurality of device pins surrounding the component pads, one or more of the plurality of device pins having fine-pitch conductive paths coupling the one or more of the plurality of device pins to a set of corresponding pad landings or to a set of corresponding component pads, the fine-pitch conductive paths traversing regions between the plurality of component pads; and
wherein the fine pitch conductive paths are routed in the range of about 80 μm to about 150 μm in terms of cumulative line width and spacing.
3. A semiconductor device comprising:
an underside layer having openings;
a carrier having a first side opposite a second side, wherein the first side includes a conductive layer having a predetermined pattern that defines a number of mutually isolated connection conductors, and wherein the second side is in contact with the underside layer and includes contact surfaces corresponding to the connection conductors for placement over a substrate, wherein the openings in the underside layer permit access to the connection conductors;
the carrier including a cavity defined between the first and second sides, the cavity having a die pad region, the carrier further including component pad regions, the component pad regions providing for the placement of surface mount devices on the carrier, the component pad regions coupled to selected connection conductors with fine-pitch conductive paths;
an integrated circuit device including a die area located in the cavity and attached to the die pad region of the underside layer, and further including bonding pads that are wire bonded to the connection conductors;
and a passivating envelope that encapsulates the IC device and extends as far as the carrier, wherein the passivating envelope is mechanically anchored into side faces in the connection conductors.
4. The semiconductor device as recited in claim 3 , wherein the side faces have recesses, the recesses providing attachment to the passivating envelope.
5. The semiconductor device as recited in claim 4 , wherein the recesses are shaped concave or notched.
6. The semiconductor device as recited in claim 5 , wherein the conductive layer includes a first conductive layer, a second conductive layer and a third conductive layer, the second conductive layer comprising a material that can be etched in an etchant that leaves the first conductive layer and the third conductive layer substantially intact and the etchant defines recesses in the side faces of the connection conductors.
7. The semiconductor device as recited in claim 6 , wherein the fine-pitch conductive paths are defined in the first conductive layer.
8. The semiconductor device as recited in claim 5 , wherein the fine-pitch conductive paths are defined in the third conductive layer.
9. The semiconductor device as recited in claim 8 , wherein fine-pitch conductive paths are protected with a solder resist.
10. The semiconductor device as recited in claim 3 , wherein the component pad regions surround the die pad region.
11. The semiconductor device as recited in claim 3 , wherein the surface mount devices include at least one selected from the following: surface mount capacitors, surface mount resistors, surface mount inductors, integrated circuit chips, oscillators.
12. The semiconductor device as recited in claim 11 , wherein the surface mount devices are two-terminal devices.
13. The package substrate as recited in claim 7 , wherein the fine pitch conductive paths are routed at less than about 80 μm in terms of cumulative line width and spacing.
14. The package substrate as recited in claim 7 , wherein the fine pitch conductive paths are routed in the range of about 80 μm to about 150 μm in terms of cumulative line width and spacing.
15. A semiconductor device comprising:
an underside layer having openings;
a carrier having a first side opposite a second side, wherein the first side includes a conductive layer, the conductive layer including a predetermined pattern that defines a number of mutually isolated connection conductors, the conductive layer having a first conductive layer, a second conductive layer and a third conductive layer, the second conductive layer comprising a material that can be etched in an etchant that leaves the first conductive layer and the third conductive layer substantially intact and the etchant defines recesses in side faces of the connection conductors;
the second side is in contact with the underside layer and includes contact surfaces corresponding to the connection conductors for placement over a substrate, wherein the openings in the underside layer permit access to the connection conductors;
the carrier including a cavity defined between the first and second sides, the cavity having a die pad region, the carrier further including component pad regions, the component pad regions providing for the placement of surface mount devices on the carrier, the component pad regions coupled to selected connection conductors with fine-pitch conductive paths, the fine pitch conductive paths being defined in either the first conductive layer or the third conductive layer;
an integrated circuit device including a die area located in the cavity and attached to the die pad region of the underside layer, and further including bonding pads that are wire bonded to the connection conductors;
and a passivating envelope that encapsulates the IC device and extends as far as the carrier, wherein the passivating envelope is mechanically anchored into the recesses in the side faces of the connection conductors, wherein the recesses provide attachment to the passivating envelope.
16. The semiconductor device as recited in claim 15 , wherein a solder resist is applied to the underside layers in regions not having connection conductors.
17. The semiconductor device as recited in claim 16 , wherein the solder resist is applied to the fine pitch conductive paths defined in the third conductive layer, the solder resist, the solder resist sealing the fine pitch conductive paths, as the semiconductor device is soldered to a printed circuit board.