Redistribution layer for wafer-level chip scale package and method therefor
View Patent ↗In an example embodiment, there is a method for packaging an integrated circuit device (IC) having a circuit pattern ( 305 ) in a wafer-level chip-scale (WLCS) package ( 300 ). The method includes depositing a metal layer ( 5, 10, 15 ) on a first dielectric layer ( 315 ) and filling ( 20 ) in bond pad openings ( 310 ) and bump pad openings ( 330 ); the metal layer ( 360 ) has atop ( 340 ) and bottom ( 360 ) layer. In the metal layer ( 360 ), bond pad connections ( 310 ) and bump pad connections ( 330 ) are defined ( 25, 30 ) by removing the top layer of metal in areas other than at bond pad openings ( 310 ) and bump pad openings ( 330 ), and leaving the bottom layer ( 360 ) of metal in areas without bond pad or bump pad connections. In the bottom metal layer, connection traces between the bond pad and bump pad are defined ( 35, 40 ). A second organic dielectric layer ( 325 ) is deposited ( 45 ) on the silicon substrate ( 305 ), enveloping the circuit pattern. The second organic dielectric layer is removed ( 50 ) from the bump pad connections exposing the bump pads ( 330 ).
1. A method for preparing an integrated circuit device having a circuit pattern, on a silicon substrate, the circuit pattern having bond pads, for packaging in a wafer-level chip-scale (WLCS) package, the method comprising:
depositing a first organic dielectric layer on the silicon substrate, covering the circuit pattern of the IC device;
defining bond pad openings above the bond pads of the circuit pattern and bump pad openings at a predetermined distance from the bond pad openings in the first organic dielectric layer;
depositing a metal layer on the first dielectric layer and filling the bond pad openings and bump pad openings, the metal layer having a top layer of metal and a bottom layer of metal;
defining bond pad connections and bump pad connections by removing the top layer of metal in areas other than the bond pad openings and bump pad openings, and leaving the bottom layer of metal in areas not having bond pad or bump pad connections;
defining connection traces from the bond pad connections to the bump pad connections, in the bottom metal layer;
depositing a second organic dielectric layer on the silicon substrate, enveloping the circuit pattern; and
removing the second organic dielectric layer from the bump pad connections and exposing the bump pad connections.
2. The method as recited in claim 1 , wherein defining the bond pad openings and bump pad openings further includes,
applying a photo resist to mask regions of the first organic dielectric in regions other than areas defined as the bond pad openings and bump pad openings,
etching the areas defined as the bond pad openings and bump pad openings.
3. The method as recited in claim 1 , wherein defining bond pad connections and bump pad connections further includes, applying a photo resist to mask the top layer of metal over the bond pad openings and bump pad openings, the photo resist serving as an etch barrier to a top metal layer etch.
4. The method as recited in claim 3 , wherein defining connection traces further comprises, applying a photo resist to mask the bond pad and bump pad connections and mask those areas of bottom metal layer forming the connection traces between the bond pad and bump pad.
5. The method as recited in claim 4 , further including, applying solder balls to the exposed bump pad connections.
6. The method as recited in claim 5 , wherein the metal layer further includes, deposited multiple sub-layers of metal.
7. The method as recited in claim 2 , wherein, the top metal layer includes one or more metal sub-layers; and the bottom metal layer includes one or more metal sub-layers.
8. The method as recited in claim 7 , wherein the top metal layer includes metals selected from the following: Ni, V, Cu, NiV, Cr, and W.
9. The method as recited in claim 7 , wherein the bottom metal layer includes metals selected from the following: Al, Ni, V, Cu, Ti, and NiV.
10. The method as recited in claim 8 wherein, the top metal layer includes two sub-layers consisting of, NiV and Cu or Cr and W; the bottom metal layer includes four sub-layers consisting of Al, NiV, Cu, and Ti.
11. The method as recited in claim 1 , wherein the first organic and second organic dielectric layers are selected from the following: benzocyclobutene, epoxy, polyimide.
12. The method as recited in claim 4 , wherein the first organic and second organic dielectric layers are selected from the following: benzocyclobutene, epoxy, polyimide.
13. A method for preparing an integrated circuit device (IC) having a circuit pattern, on a silicon substrate, the circuit pattern having bond pads, for packaging in a wafer-level chip-scale (WLCS) package, the method comprising:
depositing a first organic dielectric layer on the silicon substrate, covering the circuit pattern of the IC device, the first organic dielectric layer selected from the following: benzocyclobutene, epoxy, polyimide;
defining bond pad openings above the bond pads of the circuit pattern and bump pad openings at a predetermined distance from the bond pad openings in the first organic dielectric layer,
wherein defining the bond pad openings and bump pad openings further comprises,
applying a photo resist to mask regions of the first organic dielectric in regions other than areas defined as the bond pad openings and bump pad openings;
etching the areas defined as the bond pad openings and bump pad openings;
depositing a metal layer on the first dielectric layer and filling the bond pad openings and bump pad openings, the metal layer having a top layer of metal and a bottom layer of metal, the top metal layer having two sub-layers including one of, NiV and Cu or Cr and W, the bottom metal layer having four sub-layers including Al, NiV, Cu, and Ti;
defining bond pad connections and bump pad connections by removing the top layer of metal in areas other than the bond pad openings and bump pad openings, and leaving the bottom layer of metal in areas not having bond pad or bump pad connections,
wherein defining bond pad connections and bump pad connections further comprises,
applying a photo resist to mask the top layer of metal over the bond pad openings and bump pad openings, the photo resist serving as an etch barrier to a top metal layer etch;
defining connection traces from the bond pad connections to the bump pad connections, in the bottom metal layer,
wherein defining connection traces further comprises,
applying a photo resist to mask the bond pad and bump pad connections and mask those areas of the bottom metal layer forming the connection traces between the bond pad and bump pad,
depositing a second organic dielectric layer on the silicon substrate,
enveloping the circuit pattern, the second organic dielectric layer selected from the following: benzocyclobutene, epoxy, polyimide; removing the second organic dielectric layer from the bump pad connections and exposing the bump pad connections; and applying solder balls to the exposed bump pad connections.
14. A wafer-level chip-scale(WLCS) package for packaging an integrated circuit device(IC), the IC having a circuit pattern on a silicon substrate, the circuit pattern having bond pads, the WLCS package comprising:
a first dielectric layer covering the circuit pattern, wherein bond pad openings are defined in the first dielectric layer over the bond pads and bump pad openings, bump pad openings are defined and located at predetermined distances from corresponding bond pad openings;
a metal redistribution layer deposited on the first dielectric layer in the bond pad openings and bump pad openings, the metal redistribution layer having mutually isolated connection traces, electrically coupling bond pads with corresponding bump pad connections defined by the metal redistribution layer in the bump pad openings, the metal redistribution layer including a top metal layer and a bottom metal layer, wherein the connection traces include only the bottom metal layer;
a second dielectric layer covering the metal redistribution layer except at bump pad connections; and
solder bumps attached to the bump pad connections.
15. The WLCS package as recited in claim 14 , wherein the top metal layer includes one or more metal sub-layers; and the bottom metal includes one or more metal sub-layers.
16. The WLCS package as recited in claim 15 , wherein the one or more metal sub-layers of the top metal layer includes metals selected from the following: Ni, V, Cu, NiV, Cr, and W; and the one or more metal sub-layers of the bottom metal layer includes metals selected from the following: Al, Ni, V, Cu, Ti, and NiV.
17. The WLCS package as recited in claim 16 , wherein the first and second dielectric layer includes materials selected from the following: benzocyclobutene, epoxy, polyimide.
18. The WLCS package as recited in claim 17 , wherein the bottom metal layer consists of four metal sub-layers of Al, Ni, NiV, and Ti; and the top metal layer consists of two metal sub-layers of NiV and Cu or Cr and W.
19. The WLCS package as recited in claim 17 , wherein the bottom metal layer consists of four metal sub-layers deposited in order of, Al, Ni, NiV, Ti; and the top metal layer consists of two metal sub-layers deposited in order of, NiV, Cu.
20. The WLCS package as recited in claim 17 , wherein the bottom metal layer consists of four metal sub-layers deposited in order of, Al, Ni, NiV, Ti; and the top metal layer consists of two metal sub-layers deposited in order of, W, Cr.