Semiconductor device and manufacturing process therefor

1. A semiconductor device, comprising:

an isolation region formed within a semiconductor substrate;

an N-type region and a P-type region formed within the semiconductor substrate such that the N-type region and the P-type region are isolated by the isolation region;

a line electrode extending from a region over the N-type region through a region over the isolation region to a region over the P-type region;

a PMOS transistor comprising a first gate insulating film formed over the N-type region and a first gate electrode which is the line electrode over the N-type region; and

an NMOS transistor comprising a second gate insulating film formed over the P-type region and a second gate electrode which is the line electrode over the P-type region,

wherein the line electrode comprises an electrode section (A) comprising the first gate electrode, an electrode section (B) comprising the second gate electrode and a diffusion barrier region formed for preventing contact of the electrode sections (A) and (B) over the isolation region,

wherein the diffusion barrier region contains an element different from elements in the electrode sections (A) and (B), and the electrode sections (A) and (B) are made of materials containing mutually different elements or of materials containing the same elements in a different composition,

wherein the diffusion barrier region meets the following conditions (1) and (2):

(1) a diffusion coefficient D 1 of a constituent element A′ of the electrode section (A) in the diffusion barrier region is lower than an interdiffusion coefficient D 2 of the constituent element A′ between the electrode section (A) materials;

(2) a diffusion coefficient D 3 of a constituent element B′ of the electrode section (B) in the diffusion barrier region is lower than an interdiffusion coefficient D 4 of the constituent element B′ between the electrode section (B) materials,

wherein the electrode sections (A) and (B) as well as the diffusion barrier region are made of a silicide, and

wherein the silicide constituting the diffusion barrier region is a silicide containing a metal element which becomes a diffusing species to silicon during a siliciding reaction.

2. The semiconductor device as claimed in claim 1 ,

wherein the silicide constituting the diffusion barrier region is a silicide of at least one metal element selected from the group consisting of Pt, Pd, Co and Ni.

3. The semiconductor device as claimed in claim 1 ,

wherein the electrode section (A) is made of a silicide represented by Ni x Si 1-x (0.55≦x<1), and the electrode section (B) is made of a silicide represented by Ni x Si 1-x (0<x<0.55).

4. The semiconductor device as claimed in claim 3 ,

wherein the electrode section (A) is made of Ni 3 Si or Ni 2 Si, and the electrode section (B) is made of NiSi or NiSi 2 .

5. The semiconductor device as claimed in claim 1 ,

wherein the silicides constituting the electrode sections (A) and (B) are dopant-containing silicides which contain dopants consisting of mutually different elements.

6. The semiconductor device as claimed in claim 5 ,

wherein the electrode section (A) is made of NiSi containing B, Al or In as the dopant, and the electrode section (B) is made of NiSi containing P, As or Sb as the dopant.

7. The semiconductor device as claimed in claim 1 ,

wherein the silicides constituting the electrode sections (A) and (B) are a refractory metal silicide.

8. A semiconductor device, comprising:

an isolation region formed within a semiconductor substrate;

an N-type region and a P-type region formed within the semiconductor substrate such that the N-type region and the P-type region are isolated by the isolation region;

a line electrode extending from a region over the N-type region through a region over the isolation region to a region over the P-type region;

a PMOS transistor comprising a first gate insulating film formed over the N-type region and a first gate electrode which is the line electrode over the N-type region; and

an NMOS transistor comprising a second gate insulating film formed over the P-type region and a second gate electrode which is the line electrode over the P-type region,

wherein the line electrode comprises an electrode section (A) comprising the first gate electrode, an electrode section (B) comprising the second gate electrode and a diffusion barrier region formed for preventing contact of the electrode sections (A) and (B) over the isolation region,

wherein the diffusion barrier region contains an element different from elements in the electrode sections (A) and (B), and the electrode sections (A) and (B) are made of materials containing mutually different elements or of materials containing the same elements in a different composition,

wherein the diffusion barrier region meets at least one of the following conditions (1) and (2):

(1) a diffusion coefficient D 1 of a constituent element A′ of the electrode section (A) in the diffusion barrier region is lower than an interdiffusion coefficient D 2 of the constituent element A′ between the electrode section (A) materials;

(2) a diffusion coefficient D 3 of a constituent element B′ of the electrode section (B) in the diffusion barrier region is lower than an interdiffusion coefficient D 4 of the constituent element B′ between the electrode section (B) materials, and

wherein the electrode sections (A) and (B) as well as the diffusion barrier region contain the same metal element M 1 , and

wherein the diffusion barrier region is made of a silicide of the metal element M 1 , and the metal element M 1 is such an element that in a siliciding reaction of the metal element M 1 , silicon is a diffusing species to the metal element M 1 ,

wherein the diffusion barrier region meets only the condition (1),

the metal element M 1 is Ru, and

the electrode section (A) and the electrode section (B) are made of RuTa and Ru, respectively.

9. The semiconductor device as claimed in claim 1 ,

wherein the first and the second gate insulating films are a high-dielectric insulating film.

10. The semiconductor device as claimed in claim 1 ,

wherein the NMOS transistor and the PMOS transistor constitute a CMOS transistor.

11. A process for manufacturing the semiconductor device as claimed in claim 1 , comprising:

preparing the semiconductor substrate comprising the N-type region and the P-type region which are isolated by the isolation region;

forming a gate insulating film on the semiconductor substrate;

forming a polysilicon gate pattern extending from a region over the N-type region through a region over the isolation region to a region over the P-type region;

forming a mask over the gate pattern;

removing a part of the mask formed on the gate pattern over the isolation region to expose the polysilicon;

depositing a layer of a silicide-formable metal M 2 on the exposed polysilicon;

reacting the metal M 2 and the polysilicon by heating to form the diffusion barrier region such that a silicide of the metal M 2 is formed until it comes into contact with the gate insulating film over the isolation region and the silicide of the metal M 2 is absent over the N-type region and the P-type region, as a first siliciding step;

removing the layer of the metal M 2 which is unreacted with the polysilicon during the first siliciding step; and

converting gate pattern sections over the N-type region and over the P-type region which are separated by the diffusion barrier region into the electrode sections (A) and (B) made of a silicide, respectively, as a second siliciding step.

12. The process for manufacturing the semiconductor device as claimed in claim 11 ,

wherein the metal M 2 is Pt, and

the second siliciding step comprises:

removing the mask remaining on the gate pattern sections over the N-type and P-type regions;

depositing an Ni layer on the gate patterns;

reacting the polysilicon constituting the gate pattern sections over the N-type and the P-type regions with the Ni by heating to form NiSi regions;

removing the Ni layer unreacted with the polysilicon;

forming a mask on the NiSi region over the P-type region;

depositing an Ni layer on the NiSi region over the N-type region;

reacting the NiSi constituting the NiSi region over the N-type region with the Ni by heating to form Ni 3 Si;

removing the Ni layer unreacted with the NiSi; and

removing the mask formed on the NiSi region over the P-type region.

13. The process for manufacturing the semiconductor device as claimed in claim 11 ,

wherein in forming the gate pattern, dopant-containing polysilicons are formed such that the dopant-containing polysilicons over the N-type and the P-type regions contain dopants consisting of different elements, as the polysilicon,

the metal M 2 is Pt, and

the second siliciding step comprises:

removing the mask remaining on the gate pattern sections over the N-type and P-type regions;

depositing an Ni layer on the gate patterns;

reacting dopant-containing polysilicons constituting the gate pattern sections over the N-type and the P-type regions with the Ni by heating, respectively, to form dopant-containing NiSi regions; and

removing the Ni layer unreacted with the dopant-containing polysilicon.

14. The process for manufacturing the semiconductor device as claimed in claim 11 ,

wherein the metal M 2 is Co, and

the second siliciding step comprises:

removing the mask formed on the gate pattern section over the N-type region;

depositing an Mo layer on the gate pattern section over the N-type region;

reacting the Mo with the polysilicon constituting the gate pattern section over the N-type region by heating to form MoSi 2 ;

removing the Mo layer unreacted with the polysilicon;

removing the mask formed on the gate pattern section over the P-type region;

depositing a Hf layer on the gate pattern section over the P-type region;

reacting the Hf with the polysilicon constituting the gate pattern section over the P-type region by heating to form HfSi; and

removing the Hf layer unreacted with the polysilicon.

15. A process for manufacturing the semiconductor device as claimed in claim 1 , comprising:

preparing the semiconductor substrate comprising the N-type region and the P-type region which are isolated by the isolation region;

forming a gate insulating film on the semiconductor substrate;

forming a polysilicon gate pattern extending from a region over the N-type region through a region over the isolation region to a region over the P-type region;

forming a mask over the gate pattern;

removing the mask formed on gate pattern sections over the N-type and the P-type regions to expose the polysilicon;

depositing a layer of a silicide-formable metal M 3 on the exposed polysilicon;

reacting the metal M 3 with the exposed polysilicon by heating to converting at least part of the gate pattern sections over the N-type and the P-type regions into metal M 3 silicide regions such that the gate pattern sections of the N-type and the P-type regions are not mutually communicated over the isolation region, as a third siliciding step;

removing the layer of the metal M 3 unreacted with the polysilicon during the third siliciding step;

removing the mask remaining on the gate pattern over the isolation region to expose the polysilicon;

depositing a layer of a silicide-formable metal M 4 on the exposed polysilicon;

reacting the metal M 4 with the exposed polysilicon by heating to form the diffusion barrier region such that a silicide of the metal M 4 is formed until it comes into contact with the gate insulating film over the isolation region and the silicide of the metal M 4 is absent over the N-type region and the P-type region, as a fourth siliciding step;

removing the layer of the metal M 4 unreacted with the polysilicon during the fourth siliciding step; and converting the metal M 3 silicide regions over the N-type and the P-type regions into the electrode sections (A) and (B), respectively, as a fifth siliciding step.

16. The process for manufacturing the semiconductor device as claimed in claim 15 ,

wherein the third siliciding step is reacting the metal M 3 with the upper part of the polysilicon to form an Ni 2 Si region and to leave the unreacted polysilicon in the lower part of the Ni 2 Si region,

the metal M 4 is Pt, and

the fifth siliciding step comprises:

reacting the Ni 2 Si constituting the Ni 2 Si region with the polysilicon remaining in the lower part of the Ni 2 Si region by heating to form an NiSi region;

forming a mask on the NiSi region over the P-type region;

depositing an Ni layer on the NiSi region over the N-type region;

reacting the NiSi constituting the NiSi region over the N-type region with the Ni by heating to form Ni 2 Si;

removing the Ni layer unreacted with the NiSi; and

removing the mask formed on the NiSi region over the P-type region.

17. The process for manufacturing the semiconductor device as claimed in claim 15 ,

wherein the third siliciding step is reacting the metal M 3 with all the polysilicon constituting the gate pattern sections over the N-type and the P-type regions to form an NiSi region,

the metal M 4 is Pt, and

the fifth siliciding step comprises:

forming a mask on the NiSi region over the P-type region;

depositing an Ni layer on the NiSi region over the N-type region;

reacting the NiSi constituting the NiSi region over the N-type region with the Ni by heating to form Ni 3 Si;

removing the Ni layer unreacted with the NiSi; and

removing the mask formed on the NiSi region over the P-type region.

18. The process for manufacturing the semiconductor device as claimed in claim 15 ,

wherein in forming the gate pattern, dopant-containing polysilicons are formed such that dopant-containing polysilicons over the N-type and the P-type regions contain dopants of different elements, as the polysilicon,

the third siliciding step is reacting the metal M 3 with the upper part of the dopant-containing polysilicon to form a dopant-containing Ni 2 Si region and to leave the unreacted dopant-containing polysilicon in the lower part of the dopant-containing Ni 2 Si region,

the metal M 4 is Pt, and

the fifth siliciding step comprises the step of reacting the dopant-containing Ni 2 Si constituting the dopant-containing Ni 2 Si region with the dopant-containing polysilicon remaining in the lower part of the dopant-containing Ni 2 Si region by heating to form a dopant-containing NiSi.

19. A process for manufacturing the semiconductor device as claimed in claim 1 , comprising:

preparing the semiconductor substrate comprising the N-type region and the P-type region which are isolated by the isolation region;

forming a gate insulating film on the semiconductor substrate;

forming a gate pattern made of Ru extending from a region over the N-type region through a region over the isolation region to a region over the P-type region;

forming a mask over the gate pattern;

removing a part of the mask formed on the gate pattern over the isolation region to expose the Ru;

depositing a silicon layer on the exposed Ru;

reacting the Ru with the silicon by heating to form the diffusion barrier region such that a silicide of the Ru is formed until it comes into contact with the gate insulating film over the isolation region and the silicide of Ru is absent over the N-type region and the P-type region, as a sixth siliciding step;

removing the silicon layer unreacted with the Ru in the sixth siliciding step;

removing the mask remaining on the gate pattern section over the N-type region;

depositing a Ta layer on the gate pattern section over the N-type region;

reacting the Ru constituting the gate pattern section over the N-type region with the Ta by heating to form RuTa;

removing the Ta layer unreacted with the Ru; and

removing the mask remaining on the gate pattern section over the P-type region.