IP Library Granted Patent US 8,541,776
Granted Patent B2
US 8,541,776 · App. 12/094,850 · Granted Sep 24, 2013

Nanostructure-based memory

Inventors: Prabhakar R. Bandaru (San Diego, CA); Joel Hollingsworth (San Diego, CA)
Assignee: The Regents of the University of California
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,541,776
App. No.
12/094,850
Granted
Sep 24, 2013
Kind
B2
Abstract

Improved memory devices that include one or more nanostructures such as carbon nanotubes or other nanostructures, as well as systems and devices incorporating such improved memory devices, are disclosed. In at least some embodiments, the improved memory device is of a nonvolatile type such as a flash memory device, and employs a pair of triodes that form a memory cell, where each triode employs at least one carbon nanotube. Also disclosed are methods of operating and fabricating such improved memory devices.

Claims (19)

1. A memory device comprising:

a memory cell that includes:

a first triode that includes a first nanostructure;

a second triode that includes a second nanostructure; and

a layer of metal that forms both an anode of the first triode and a cathode of the second triode;

wherein the first nanostructure and the second nanostructure are positioned within a vacuum-sealed region.

2. The memory device of claim 1 , wherein the first nanostructure is a carbon nanostructure.

3. The memory device of claim 2 , wherein the carbon nanostructure is a carbon nanotube (CNT).

4. The memory device of claim 1 , wherein the memory device is a non-volatile memory device.

5. The memory device of claim 1 , wherein the memory device is a flash memory device.

6. The memory device of claim 1 , wherein the memory device is a random access memory (RAM) device.

7. The memory device of claim 1 , wherein the memory device is a read only memory (ROM) device.

8. The memory device of claim 1 , wherein the memory device is an alternating current (AC) type device.

9. The memory device of claim 1 , wherein the memory cell includes first and second portions having first and second substrates, respectively, wherein the first and second nanostructures are fabricated on the first and second substrates, respectively, and wherein the first and second portions of the memory cell are arranged in relation to one another by way of a flip-chip operation.

10. The memory device of claim 9 , wherein the first nanostructure serves as an erase tip.

11. A logic device comprising the memory device of claim 1 .

12. A computer employing the logic device of claim 11 , wherein the logic device is a NAND gate that can be used to form at least part of a further gate selected from the group consisting of an AND gate, a NOR gate, an OR gate, an XOR gate, or another type of logic gate.

13. The device of claim 1 , wherein the first nanostructure comprises a nanotube, a nanowire, a nanocone, or a nanofiber and the second nanostructure comprises another nanotube, another nanowire, another nanocone, or another nanofiber.

14. The device of claim 1 , wherein the layer of metal forms a plate of a storage capacitor.

Assignments (2)
CONFIRMATORY LICENSE Recorded Jul 15, 2014
From: UNIVERSITY OF CALIFORNIA SAN DIEGO
To: NATIONAL SCIENCE FOUNDATION
Reel/Frame 033329/0521 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2010
From: BANDARU, PRABHAKAR; HOLLINGSWORTH, JOEL
To: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
Reel/Frame 024494/0986 →
Continuity (2)
Provisional Application 60741574 · Dec 2, 2005
Related Publication 20090175073A1 · Jul 9, 2009