Method and apparatus to reduce dynamic Rdson in a power switching circuit having a III-nitride device
A method of preventing the Rdson of a III-V Nitride power switching circuit from varying over time. The method includes biasing the switch to a pre-bias voltage level just below turn ON when the switch is OFF, wherein traps are discharged when the switch is biased to the pre-bias voltage level just below turn ON and the varying of the Rdson over time due to traps is reduced. The method can be employed in DC-DC converter circuits having III-V Nitride control and synchronous switches connected at a switching node.
1. A method of preventing the Rdson of a III-V Nitride power switch in a power switching circuit from varying over time, the method comprising biasing the power switch to a pre-bias voltage level just below turn ON when the switch is OFF, wherein traps are discharged when the switch is biased to the pre-bias voltage level just below turn ON and the varying of the Rdson over time due to traps is reduced.
2. The method of claim 1 , wherein the power switching circuit is a DC-DC converter circuit, the converter circuit including a gate driver for controlling control and synchronous power switches connected at a switching node.
3. The method of claim 1 , further comprising a step of selecting the voltage level of bias so as to set the switch being biased to just below a turn-on threshold voltage without creating a significant current conduction.
4. The method of claim 2 , wherein the voltage level of bias depends on a type and depth of the traps.
5. The method of claim 3 , further comprising a step of applying the voltage level of bias for reducing traps to the switches during ON- and OFF-times.
6. The method of claim 2 , wherein the selected voltage level of the bias and a frequency of biasing does not interfere with a normal operation of the converter circuit.
7. The method of claim 6 , further comprising a step of selecting a timing of the biasing to be shorter than a main switching cycle of the switches so as not to interfere with a dead-time control of the converter circuit.
8. The circuit of claim 2 , wherein the converter circuit further includes a cut-off switch controlled by the gate driver and connected between the control switch and a power supply, the cut-off switch turning OFF current flowing from the power supply to the control switch before a start-up of the circuit.
9. The method of claim 8 , further comprising a step of biasing the control switch while the synchronous switch is ON and the cut-off switch is OFF to turn ON the control switch to prepare it for the cut-off switch being turned ON.
10. The method of claim 1 , further comprising a step of providing a de-trapping bias either before or after the pre-bias voltage lead.
11. The method of claim 1 , further comprising alternately providing the pre-bias voltage level and the de-trapping voltage level during either or both the on time and off time of the power switch.
12. The method of claim 2 , wherein the pre-bias voltage level is applied to either or both the control switch or the synchronous switch.
13. A DC-DC converter circuit for reducing dynamic Rdson of at least one of a control and synchronous III-V Nitride power switch connected at a switching node and having gate terminals, the switches being controlled by a gate driver, wherein during a normal operation of the converter circuit after the at least one switch is controlled completely OFF the gate of the OFF switch is biased to a voltage level just below turn ON to prevent a dynamic Rdson of the switch by discharging traps.
14. The circuit of claim 13 , wherein the dynamic Rdson is a state in which the Rdson varies over time due to traps.
15. The circuit of claim 13 , wherein the voltage level of the bias is selected such that the switch is set to just below a threshold voltage and does not create significant current conduction.
16. The circuit of claim 15 , wherein the voltage level of the bias is tailored to reduce traps in a III-V Nitride switch depending on a type and depth of the traps.
17. The circuit of claim 16 , wherein the voltage level of the bias is applied to the gate of the switch during both ON- and OFF-times.
18. The circuit of claim 16 , wherein the voltage level and frequency of the bias application is selected to reduce traps without interfering with a normal operation of the converter circuit.
19. The circuit of claim 18 , wherein a timing of the bias application for reducing traps is selected to be shorter than a main switching cycle so as not to interfere with a dead-time control of the converter circuit.
20. The circuit of claim 13 , further comprises a cut-off switch having a gate terminal and being controllable by the gate driver, the cut-off switch is connected between the control switch and a power supply, the cut-off switch turning OFF current flowing from the power supply to the control switch before a start-up of the circuit.
21. The circuit of claim 20 , wherein the cut-off switch is a silicon device and the control and synchronous switches are Field-Effect Transistor (FET) device.
22. The circuit of claim 20 , wherein the voltage level of the bias is applied to the gate of the control switch while the synchronous switch is ON and the cut-off switch is OFF, the applied voltage level of the bias turning ON the control switch to prepare it for the cut-off switch being turned ON.