Semiconductor device and dummy pattern arrangement method

1. A dummy pattern arrangement method using a computer, comprising:

reading arrangement data where first and second wiring patterns are arranged in a first region, the first and second wiring patterns extending along a first axis line;

arranging one or more first dummy patterns in the first region in such a manner that the first dummy pattern extends along a second axis line different from the first axis line and is separated from the first and second wiring patterns; and

processing, by the computer, a first end of the first dummy pattern to form a first dummy land at the first wiring pattern side,

wherein the first dummy land is formed by separating both end parts of the dummy pattern.

2. The dummy pattern arrangement method according to claim 1 further comprising:

processing a second end of the first dummy pattern to form a second dummy land at the second wiring pattern side.

3. The dummy pattern arrangement method according to claim 1 , wherein a plurality of first dummy patterns are arranged in the first region and the first ends of the plurality of first dummy patterns are processed to form the first dummy lands at the first wiring pattern side.

4. The dummy pattern arrangement method according to claim 2 , wherein a plurality of first dummy patterns are arranged in the first region and the second end of the plurality of first dummy patterns are processed to form the second dummy lands at the second wiring pattern side.

5. The dummy pattern arrangement method according to claim 1 , wherein width of the first dummy land along the second axis line is narrower than width of the rest of the first dummy pattern along the second axis line.

6. The dummy pattern arrangement method according to claim 1 , wherein an end of the first dummy land is processed and a third dummy land is arranged next to the first dummy land.

7. The dummy pattern arrangement method according to claim 1 further comprising:

checking arrangement position of third wiring patterns in a second region superimposed on the first region; and

arranging the first dummy pattern in the first region so as not to overlap with the third wiring patterns.

8. The dummy pattern arrangement method according to claim 7 , wherein the second region is formed in a first wiring layer immediately above or immediately below a second wiring layer where the first region is formed.

9. The dummy pattern arrangement method according to claim 1 , further comprising:

checking arrangement position of third wiring patterns in a second region superimposed on the first region;

checking arrangement position of forth wiring patterns in a third region superimposed on the first region; and

arranging the first dummy pattern in the first region so as not to overlap with the third wiring patterns and the forth wiring patterns.

10. The dummy pattern arrangement method according to claim 9 , wherein

the second region is formed in a second wiring layer immediately above a first wiring layer where the first region is formed, and

the third region is formed in a third wiring layer immediately below the first wiring layer.

11. The dummy pattern arrangement method according to claim 7 , further comprising:

checking occupation rate of patterns in the first region; and

arranging one or more second dummy patterns in the first region so as to overlap with the third wiring patterns in the second region when the checked occupation rate is lower than a predetermined occupation rate, the second dummy patterns having widths narrower than widths of the third wiring patterns in the second region.

12. The dummy pattern arrangement method according to claim 1 , wherein the first axis line and the second axis line are substantially perpendicular to each other.