Semiconductor device
The present invention provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an interlayer insulating film. Dummy vias are formed in each layer on a dicing region side. The dummy vias are formed at the same intervals in a matrix as viewed in a top view. Even in the case where cracking occurs at the time of dicing, the cracking can be prevented from spreading to a seal ring by the dummy vias. As a result, resistance to moisture absorbed in a circuit formation region can be improved, and deterioration in reliability can be prevented.
1. A semiconductor device comprising:
a first interlayer insulating film having a specific dielectric constant of 3 or less;
a first insulating film on the first interlayer insulating film;
a seal ring formed within the first interlayer insulating film and the first insulating film so as to surround a circuit formation region;
a plurality of first dummy metals which are formed as a first zig zag array of columns within the first interlayer insulating film in a dicing region of a semiconductor chip and are arranged on one side of a dummy slit in a first region outside the seal ring;
the dummy slit which is surrounding the first region, the seal ring and the plurality of first dummy metals and is formed within the first interlayer insulating film in the dicing region of the semiconductor chip; and
a plurality of second dummy metals which are formed as a second zig zag array of columns within the first interlayer insulating film in the dicing region of the semiconductor chip and are arranged on an opposite side of the dummy slit in a second region outside the dummy slit,
wherein the columns of each of the first and second zig zag arrays are disposed in mutually offset lines so that columns of one line are opposite spaces between columns in another line, and
wherein each of the seal ring, the plurality of first dummy metals, the dummy slit, and the plurality of second dummy metals includes Cu material.
2. The semiconductor device according to claim 1 ,
wherein a diameter of each of the columns of the plurality of first and second dummy metals is 1 to 20 times greater than a minimum dimension, and
wherein the minimum dimension means a dimension defined as a diameter of vias and a width of interconnections that are designed as vias and the interconnections formed in respective layers.
3. The semiconductor device according to claim 1 ,
wherein the seal ring is formed in a vicinity of an edge of the semiconductor chip,
wherein the dicing region is arranged outside the seal ring,
wherein the first insulating film includes a film selected from a SiN and a SiC, and
wherein the plurality of second dummy metals surround said seal ring.
4. The semiconductor device according to claim 1 , wherein the zig zag arrays periodically repeat with a planar-view periodic shape of a parallelogram having an acute angle.
5. The semiconductor device according to claim 1 , wherein
the dummy slit forms a second seal surrounding the first region, where the seal ring forms a first seal surrounding the circuit formation region, and
the first and second seals extend from a base interlayer insulating film up through a topmost interlayer insulating film of the semiconductor device, where a passivation film and an interconnecting layer are formed on the topmost interlayer insulating film.
6. The semiconductor device according to claim 5 , wherein
the first and second zig zag arrays of columns extend from the base interlayer insulating film up through the topmost interlayer insulating film of the semiconductor device.