IP Library Granted Patent US 7,812,446
Granted Patent B2
US 7,812,446 · App. 12/107,795 · Granted Oct 12, 2010

Semiconductor device

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Quick Facts
Patent No.
US 7,812,446
App. No.
12/107,795
Granted
Oct 12, 2010
Kind
B2
Abstract

A method of manufacturing a semiconductor device including a PMOS transistor and a NMOS transistor is described. The method facilitates obtaining a FUSI phase of a suitable composition for the NMOS transistor and the PMOS transistor respectively, with fewer mask layers and through a fewer number of manufacturing steps.

Claims (44)

1. A semiconductor device comprising:

a first semiconductor chip including a plurality of first functional blocks each serving as a unit circuit that performs a specific function;

a plurality of first communication paths respectively connected to each of said plurality of first functional blocks, to be used for inputting and outputting to and from each of said plurality of first functional blocks; and

an interposer that supports said first semiconductor chip,

wherein said first communication paths are provided so as to penetrate through said interposer in a thicknesswise direction thereof.

2. The semiconductor device according to claim 1 ,

wherein said first semiconductor chip includes a communication path provided among said plurality of first functional blocks

3. The semiconductor device according to claim 1 ,

wherein said interposer further includes a second communication path serving as a communication path between said first semiconductor chip and an external device.

4. The semiconductor device according to claim 1 ,

wherein said interposer further includes a first power supply path through which power is to be supplied to said first semiconductor chip.

5. The semiconductor device according to claim 1 ,

wherein said first functional block is a processor core; and

said first semiconductor chip is a processor chip including a plurality of processor cores.

6. The semiconductor device according to claim 1 , further

including a second semiconductor chip,

wherein said second semiconductor chip is provided on a second surface opposite to a first surface on which said first semiconductor chip is provided; and

said first and said second semiconductor chip are mutually connected through said first communication path.

7. The semiconductor device according to claim 6 ,

wherein said second semiconductor chip includes a plurality of second functional blocks each serving as a unit circuit that performs a specific function; and

each of said second functional blocks is electrically connected to one of said plurality of first functional blocks different from one another, through said first communication path.

8. The semiconductor device according to claim 7 ,

wherein said second functional block is a memory core; and

said second semiconductor chip is a memory chip including a plurality of memory cores.

9. The semiconductor device according to claim 8 ,

wherein said second semiconductor chip includes a plurality of memory chips stacked on one another.

10. The semiconductor device according to claim 6 ,

wherein said second semiconductor chip includes a plurality of second functional blocks; and

said plurality of second functional blocks is shared by said first functional blocks.

11. The semiconductor device according to claim 10 ,

wherein said second functional block is a memory core; and

said second semiconductor chip is a memory chip including a plurality of memory cores.

12. The semiconductor device according to claim 11 ,

wherein said second semiconductor chip includes a plurality of memory chips stacked on one another.

13. The semiconductor device according to claim 6 ,

wherein said interposer further includes a third communication path serving as a communication path between said second semiconductor chip and an external device.

14. The semiconductor device according to claim 6 ,

wherein said interposer extends further outward from at least one of said first and second semiconductor chips.

15. The semiconductor device according to claim 6 ,

wherein said interposer further includes a second power supply path through which power is to be supplied to said second semiconductor chip.

16. The semiconductor device according to claim 1 ,

wherein said interposer is constituted essentially of an insulating material.

17. The semiconductor device according to claim 1 ,

wherein said interposer is free from including an active element.

Assignments (3)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
CHANGE OF NAME Recorded Oct 28, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025214/0696 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 23, 2008
From: KURITA, YOICHIRO
To: NEC ELECTRONICS CORPORATION
Reel/Frame 020841/0684 →