Ground straddling in PTH pinfield for improved impedance
High-speed communication links are improved by having differential pairs of traces in a connector pinfield on layers of a multilayer printed circuit board (PCB) to straddle respective rows of reference (ground) pins rather than the respective rows of signal vias. Thus, a desirable increase in the size of each an anti-pad to surrounding each signal via pad can be incorporated without forcing tracing of adjacent differential pairs closer to one another, and thus increased cross talk is avoided. Thereby, 50 ohm or close to 50 ohm impedance for each signal via is achieved. Spacing and routing between traces of each differential pair are advantageously adjusted for skew compensation and impedance optimization utilizing three dimensional computational electromagnetic tools.
1. A printed circuit board for a communication connector, comprising:
a pinfield of a rectangularly spaced array of signal vias and an interspersed rectangularly spaced array of reference vias, arranged such that each signal via, which is not at an edge of the array of signal vias, is centered among four adjacent reference vias;
a differential pair of traces aligned so that a first trace passes on one side of a centerline passing through a row of reference vias and a second trace passes on the other side of the centerline; and
first and second terminations respectively of the first and second traces at selected respective signal vias in a row of signal vias adjacent to the row of reference vias.
2. The printed circuit board of claim 1 , further comprising:
a substrate;
a ground plane affixed to the substrate;
an aperture formed in the ground plane surrounding each signal via; and
an anti-pad composed of a dielectric insulating material sized for the aperture,
wherein the aperture and anti-pad are sized to approach a 50 ohm single ended impedance by a respective trace.
3. The printed circuit board of claim 1 , further comprising each trace routed hemispherically around each reference via to a diameter permitted without routing over an anti-pad in an aperture surrounding each respective signal via.
4. The printed circuit board of claim 1 , further comprising the first trace having a longer path length in the pinfield than the second trace that comprises an added path undulations in a region of the circuit board outside of the pinfield for skew compensation.
5. The printed circuit board of claim 1 , further comprising the differential pair of traces spaced in the pinfield in accordance with a three dimension computational electromagnetic algorithm to optimize an overall impedance for the differential pair.
6. The printed circuit board of claim 5 , further comprising the differential pair of traces spaced in a ground straddling alignment to approximately a 50 ohm impedance single-ended and approximately a 100 ohm impedance differentially.
7. An apparatus having optimizing impedance of differential pairs of traces on a plated through holes pinfield of a circuit board, comprising:
on a pinfield of a rectangularly spaced array of signal vias and an interspersed rectangularly spaced array of reference vias, such that each signal via, which is not at an edge of the array of signal vias, is centered among four adjacent reference vias, means for aligning a differential pair of traces so that a first trace passes on one side of a centerline passing through a row of reference vias and a second trace passes on the other side of the centerline; and
means for terminating the first and second traces at selected respective signal vias in a row of signal vias adjacent to the row of reference vias.
8. The apparatus of claim 7 , further comprising means for enlarging along a row centerline an aperture in a conductive ground plane surrounding each signal via and widening the aperture to a diameter that prevents a signal straddling layout of a differential pair of traces, thereby increasing signal via impedance.
9. The apparatus of claim 7 , further comprising means for routing each trace hemispherically around each reference via to a diameter permitted without routing over an anti-pad in an aperture surrounding each respective signal via.
10. The apparatus of claim 7 , further comprising means for adding path undulations to a selected trace of the differential pair in a region of the circuit board outside of the pinfield for skew compensation.
11. The apparatus of claim 7 , further comprising means for spacing the traces of the differential pair in the pinfield in accordance with a three dimension computational electromagnetic algorithm to optimize an overall impedance for the differential pair.
12. The apparatus of claim 11 , further comprising means for spacing the traces of the differential pair in a ground straddling alignment to approximately a 50 ohm impedance single-ended and approximately a 100 ohm impedance differentially.
13. A method of optimizing impedance of differential pairs of traces on a plated through holes pinfield of a circuit board, comprising:
on a pinfield of a rectangularly spaced array of signal vias and an interspersed rectangularly spaced array of reference vias, such that each signal via, which is not at an edge of the array of signal vias, is centered among four adjacent reference vias, aligning a differential pair of traces so that a first trace passes on one side of a centerline passing through a row of reference vias and a second trace passes on the other side of the centerline; and
terminating the first and second traces at selected respective signal vias in a row of signal vias adjacent to the row of reference vias.
14. The method of claim 13 , further comprising enlarging along a row centerline an aperture in a conductive ground plane surrounding each signal via and widening the aperture to a diameter that prevents a signal straddling layout of a differential pair of traces, thereby increasing signal via impedance.
15. The method of claim 13 , further comprising routing each trace hemispherically around each reference via to a diameter permitted without routing over an anti-pad in an aperture surrounding each respective signal via.
16. The method of claim 13 , further comprising adding path undulations to a selected trace of the differential pair in a region of the circuit board outside of the pinfield for skew compensation.
17. The method of claim 13 , further comprising spacing the traces of the differential pair in the pinfield in accordance with a three dimension computational electromagnetic algorithm to optimize an overall impedance for the differential pair.
18. The method of claim 17 , further comprising spacing the traces of the differential pair in a ground straddling alignment to approximately a 50 ohm impedance single-ended and approximately a 100 ohm impedance differentially.