Nonvolatile semiconductor memory

1. A semiconductor memory device comprising:

a memory cell array having memory cell units each formed by connecting a plurality of memory cells;

a first and a second select gate transistors, the first select gate transistor being connected between one end of the memory cell array and a common source line, the second select gate transistor being connected between the other end of the memory cell array and bit lines;

word lines acting also as control gates of the memory cells;

a first select gate voltage-generating circuit for generating a first select gate voltage;

a second select gate-setting circuit for setting an instructed value of a second select gate voltage;

a second select gate voltage-generating circuit for generating the second select gate voltage based on the set, instructed value;

a transfer circuit for transferring the first select gate voltage generated by the first select gate voltage-generating circuit to the second select gate;

a discharging circuit for discharging the first select gate voltage transferred to the second select gate; and

a discharging characteristics selection circuit for selecting discharging characteristics of the discharging circuit.

2. The semiconductor memory device of claim 1 , wherein said discharging circuit has a plurality of discharge paths in which different discharging currents flow.

3. The semiconductor memory device according to claim 2 , wherein said discharging circuit further includes a transistor producing a discharging current that varies according to a gate voltage.

4. The semiconductor memory device according to claim 2 , wherein said discharging characteristics selection circuit controls the discharging current according to the set value of the second select gate voltage.

5. The semiconductor memory device according to claim 4 , wherein said discharging characteristics selection circuit selects the discharging characteristics of said discharging circuit in such a way that as the set value of the second select gate voltage decreases, the discharging current increases.

6. The semiconductor memory device according to claim 2 , wherein said discharging characteristics selection circuit selects one or more out of said plurality of discharge paths according to the value set by the second select gate voltage-setting circuit.

7. The semiconductor memory device according to claim 5 , wherein said discharging characteristics selection circuit selects one or more out of said plurality of discharge paths according to the value set by the second select gate voltage-setting circuit.

8. The semiconductor memory device according to claim 5 , wherein said discharging characteristics selection circuit selects the gate voltage of the second select gate transistor according to the value set by the second select gate voltage-setting circuit.

9. The semiconductor memory device according to claim 8 , wherein said discharging characteristics selection circuit shortens a discharging time of said discharging circuit with increasing the value set by the second select gate voltage-setting circuit.

10. The semiconductor memory device according to claim 9 , wherein said memory cell array is a NAND flash memory having floating gates and control gates.