Passive mixer and four phase clocking method and apparatus
According to one embodiment, a radio frequency receiver includes a quadrature mixer for converting radio frequency signals to baseband signals or intermediate frequency signals. The quadrature mixer includes an in-phase passive mixer and a quadrature-phase passive mixer. Each passive mixer includes a mixer core having a plurality of mixer input switch transistors and a plurality of output switch transistors connected to the mixer input switch transistors. Clock circuitry generates a first set of clock signals and a second set of clock signals. The first set of clock signals has a frequency twice that of the second set of clock signals. The first set of clock signals is arranged to drive the mixer input switch transistors and the second set of clock signals is arranged to drive the output switch transistors.
1. A radio frequency receiver, comprising:
a down-conversion quadrature mixer configured to down-convert radio frequency signals to baseband signals or intermediate frequency signals, the quadrature mixer comprising an in-phase passive mixer and a quadrature-phase passive mixer, wherein each of the passive mixers comprises at least one mixer core having a plurality of mixer input switch transistors and a plurality of output switch transistors connected to the mixer input switch transistors;
clock circuitry configured to generate a first set of clock signals and a second set of clock signals, the first set of clock signals having a frequency twice that of the second set of clock signals; and
wherein the first set of clock signals are arranged to drive the mixer input switch transistors and the second set of clock signals are arranged to drive the output switch transistors.
2. The radio frequency receiver of claim 1 , wherein the first and second sets of clock signals comprise pulse clock signals or sinusoidal clock signals.
3. The radio frequency receiver of claim 1 , wherein the first set of clock signals has a duty cycle of approximately 50%.
4. The radio frequency receiver of claim 1 , wherein the second set of clock signals has a duty cycle of approximately 25% to 50%.
5. The radio frequency receiver of claim 1 , wherein the at least one mixer core comprises two input switch transistors and four output switch transistors, each of the input switch transistors being connected to two of the output switch transistors.
6. The radio frequency receiver of claim 1 , wherein the at least one mixer core comprises four input switch transistors and four output switch transistors, each of the input switch transistors being connected to a different one of the output switch transistors.
7. The radio frequency receiver of claim 1 , wherein each of the passive mixers comprises an N-mixer having NMOS transistors, a P-mixer having PMOS transistors or a complementary mixer having an N-mixer and a P-mixer.
8. The radio frequency receiver of claim 1 , further comprising:
one or more capacitors arranged to capacitively couple the first and/or second set of clock signals to the passive mixers; and
bias circuitry configured to adjust a conducting time slot of the passive mixers.
9. The radio frequency receiver of claim 8 , further comprising clock buffer circuitry configured to buffer the first and/or second set of clock signals before the clock signals are capacitively coupled to the passive mixers.
10. The radio frequency receiver of claim 9 , where the clock buffer circuitry comprises one or more tank resonators.
11. A method of down-converting radio frequency signals to baseband signals or intermediate frequency signals, comprising:
providing an in-phase down-conversion passive mixer and a quadrature-phase down-conversion passive mixer, wherein each of the passive mixers comprises at least one mixer core having a plurality of mixer input switch transistors and a plurality of output switch transistors connected to the mixer input switch transistors;
generating a first set of clock signals and a second set of clock signals, the first set of clock signals having a frequency twice that of the second set of clock signals; and
driving the mixer input switch transistors with the first set of clock signals and the output switch transistors with the second set of clock signals.
12. The method of claim 11 , wherein generating the first and second sets of clock signals comprises generating pulse clock signals or sinusoidal clock signals.
13. The method of claim 11 , wherein the first set of clock signals has a duty cycle of approximately 50%.
14. The method of claim 11 , wherein the second set of clock signals has a duty cycle of approximately 25% to 50%.
15. The method of claim 11 , wherein the at least one mixer core comprises two input switch transistors and four output switch transistors, each of the two input switch transistors being connected to two of the output switch transistors and driven by the same clock signal.
16. The method of claim 11 , wherein the at least one mixer core comprises four input switch transistors and four output switch transistors, each of the four input switch transistors being connected to a different one of the output switch transistors and driven by the same clock signal.
17. The method of claim 11 , wherein the at least one mixer core comprises two output switch transistors driven by a first clock signal and two output switch transistors driven by a second clock signal.
18. The method of claim 11 , further comprising:
capacitively coupling the first and/or second set of clock signals to the passive mixers; and
adjusting a conducting time slot of the passive mixers.
19. The method of claim 18 , further comprising buffering the first and/or second set of clock signals before the clock signals are capacitively coupled to the passive mixers.