Efficient sense command generation
View Patent ↗In one embodiment, a memory includes: an array of memory cells arranged according to word lines and columns, each column corresponding to bit lines; a sense amplifier adapted to couple to the bit lines to sense a binary content of selected cells from the array of memory cells, the sense amplifier sensing the binary content responsive to a sense command; an x-decoder configured to assert a selected one of the word lines in response to decoding an address as triggered by a clock edge, wherein the assertion of the selected word line switches on corresponding access transistors to develop voltages on the bit lines; and a bit line replica circuit adapted to replicate the development of the bit lines, the bit line replica circuit including a replica access transistor coupled between a replica bit line and a replica memory cell wherein the replica access transistor is switched on responsive to the clock edge such that the replica memory cell pulls the replica bit line to ground, the bit line replica circuit also including a comparator that asserts an output in response to comparing a voltage of the replica bit line to a threshold, the sense command being a buffered version of the output from the comparator.
1. A memory, comprising:
an array of memory cells arranged according to word lines and columns, each column corresponding to bit lines;
a sense amplifier adapted to couple to the bit lines to sense a binary content of selected cells from the array of memory cells, the sense amplifier sensing the binary content responsive to a sense command;
an x-decoder configured to assert a selected one of the word lines in response to decoding an address as triggered by a clock edge, wherein the assertion of the selected word line switches on access transistors to develop voltages on the bit lines; and
a bit line replica circuit adapted to replicate the development of the bit lines, the bit line replica circuit including a replica access transistor coupled between a replica bit line and a replica memory cell, wherein the replica access transistor is switched on responsive to the clock, the bit line replica circuit further including a comparator that asserts an output in response to comparing a voltage of the replica bit line to a threshold, the sense command being a buffered version of the output from the comparator and being delayed with regard to the comparator output assertion by a buffering delay that replicates a word line development delay for the memory.
2. The memory of claim 1 , wherein the memory is a static random access memory (SRAM).
3. The memory of claim 1 , wherein the memory is a dynamic random access memory (DRAM).
4. The memory of claim 1 , further comprising a buffer to produce the sense command from the output of the comparator.
5. The memory of claim 1 , wherein the electrical characteristics of the replica memory cell are matched to the electrical characteristics of the memory cells in the array.
6. The memory of claim 1 , wherein the electrical characteristics of the replica memory cell are proportional to the electrical characteristics of the memory cells in the array.
7. The memory of claim 1 , wherein the x-decoder includes a dynamic NOR node that determines the logical state of a dynamic OR node.
8. The memory of claim 1 , wherein the bit line replica the replica memory cell comprises a plurality of replica memory cells coupled to the replica bit line through corresponding switches.