Semiconductor device and method of forming the same
View Patent ↗A semiconductor device may include an n-MOS transistor, and a p-MOS transistor. The p-MOS transistor may include, but is not limited to, a gate insulating film and a gate electrode. The gate electrode may have an adjacent portion that is adjacent to the gate insulating film. The adjacent portion may include a polysilicon that contains an n-type dopant and a p-type dopant.
1. A semiconductor device, comprising:
an n-MOS transistor formed in a substrate; and
a p-MOS transistor formed in the substrate that comprises a gate insulating film and a gate electrode, the gate electrode having an adjacent portion that is adjacent to the gate insulating film, the adjacent portion comprising a polysilicon that contains a composition of both n-type and p-type dopants, and an upper portion formed on the adjacent portion, the upper portion comprising a polysilicon that contains a composition of p-type dopant.
2. The semiconductor device according to claim 1 , wherein the adjacent portion has a thickness of at least 30 nanometers from the interface between the gate electrode and the gate insulating film.
3. The semiconductor device according to claim 1 , wherein the adjacent portion has a compositional ratio of the n-type dopant to the p-type dopant in the range of 10% to 40%.
4. The semiconductor device according to claim 1 , wherein the upper portion is free of the n-type dopant.
5. A semiconductor device, comprising:
a semiconductor substrate having an n-MOS transistor region and a p-MOS transistor region;
a gate insulating film on a surface of the semiconductor substrate, the gate insulating film being deposited on the n-MOS transistor region and the p-MOS transistor region;
a first gate electrode on the gate insulating film, the first gate electrode being located in the n-MOS transistor region, the first gate electrode comprising a first polysilicon layer containing an n-type dopant;
a second gate electrode on the gate insulating film, the second gate electrode being located in the p-MOS transistor region, the second gate electrode comprising a second polysilicon layer containing a p-type dopant;
first source/drain electrodes on the surface of the semiconductor substrate, the first source/drain electrodes being located in the n-MOS transistor region, the first source/drain electrodes containing an n-type dopant; and
second source/drain electrodes on the surface of the semiconductor substrate, the second source/drain electrodes being located in the p-MOS transistor region, the second source/drain electrodes containing a p-type dopant,
wherein the second polysilicon layer comprises a first portion on the gate insulating film and a second portion on the first portion, the first portion comprising an n-type dopant and the p-type dopant, and the second portion comprising the p-type dopant.
6. The semiconductor device according to claim 5 , wherein a thickness ratio of the first portion to a total thickness of the first portion and the second portion of the second polysilicon layer is from 10% to 50%.
7. The semiconductor device according to claim 6 , wherein a thickness of the first portion of the second polysilicon layer is less than 30 nanometers.
8. The semiconductor device according to claim 5 , wherein a compositional ratio of the n-type dopant to the p-type dopant in the first portion of the second polysilicon layer is from 10% to 40%.
9. The semiconductor device according to claim 8 , wherein a concentration of the n-type dopant in the first portion of the second polysilicon layer is from 1E19 atoms/cm 3 to 1E21 atoms/cm 3 .
10. The semiconductor device according to claim 5 , wherein the first polysilicon layer includes the n-type dopant being introduced into the first source/drain electrodes, and the second polysilicon layer includes the p-type dopant being introduced into the second source/drain electrodes.
11. The semiconductor device according to claim 5 , wherein the second portion is free of the n-type dopant.
12. A semiconductor device comprising:
an n-MOS transistor; and
a p-MOS transistor that comprises a gate insulating film and a gate electrode, the gate electrode having an adjacent portion that contacts the gate insulating film, the adjacent portion comprising a polysilicon that contains both an n-type dopant and a p-type dopant, the n-type dopant and the p-type dopant each being present throughout an entire gate length of said adjacent portion.
13. The semiconductor device according to claim 12 , wherein the gate electrode comprises a lower layer constituting the adjacent portion and an upper layer that contains the p-type dopant but is free of the n-type dopant.
14. The semiconductor device according to claim 12 , wherein the adjacent portion has a thickness of at least 30 nanometers from the interface between the gate electrode and the gate insulating film.