Granted Patent B2

US 8,344,443 · App. 12/109,736 · Granted Jan 1, 2013

Abstract

Claims (36)

1. A single-poly non-volatile memory device formed over a substrate, comprising:

a PMOS select transistor comprising a select gate formed over a select gate dielectric layer, and P+ source and drain regions formed in a shared n-well region of the substrate;

a PMOS floating gate transistor serially connected to the PMOS select transistor, where the PMOS floating gate transistor comprises a first part of a p-type floating gate layer formed over a floating gate dielectric layer, and P+ source and drain regions formed in the shared n-well region of the substrate; and

a coupling capacitor formed over a p-well region of the substrate and connected to the PMOS floating gate transistor, comprising a first capacitor plate formed with a second part of the p-type floating gate layer, a capacitor dielectric layer, and a second capacitor plate formed with an underlying portion of the p-well region.

2. The single-poly non-volatile memory device of claim 1 , where the P+ source region of the PMOS floating gate transistor is electrically connected to the P+ drain region of the PMOS select transistor.

3. The single-poly non-volatile memory device of claim 1 , where the p-type floating gate layer comprises a layer of p-type doped polysilicon that extends as a continuous conductive layer over the shared n-well region and the p-well region.

4. The single-poly non-volatile memory device of claim 1 , where the single-poly non-volatile memory device comprises an electrically erasable programmable read only memory bitcell.

5. The single-poly non-volatile memory device of claim 1 , where the PMOS floating gate transistor is a single-gate transistor without any control gate formed above the first part of the p-type floating gate layer.

6. The single-poly non-volatile memory device of claim 1 , comprising an isolation region formed in an upper region of the substrate to electrically isolate one or more active regions in the n-well region from one or more active regions in the p-well region.

7. The single-poly non-volatile memory device of claim 1 , further comprising additional single-poly non-volatile memory devices formed over the substrate in an array, where each additional single-poly non-volatile memory device comprises:

an additional PMOS select transistor formed on the shared n-well region of the substrate;

an additional PMOS floating gate transistor serially connected to the additional PMOS select transistor and formed on the shared n-well region of the substrate, where the additional PMOS floating gate transistor comprises a first part of a p-type floating gate layer; and

an additional coupling capacitor formed over the p-well region of the substrate, comprising a first additional capacitor plate formed with a second part of the p-type floating gate layer, an additional capacitor dielectric layer, and an second additional capacitor plate formed with underlying portion of the p-well region.

8. The single-poly non-volatile memory device of claim 1 , where charge on the p-type floating gate layer is erased using tunneling by applying a first relatively high voltage to the shared n-well region, the select gate, the P+ source region of the PMOS select transistor, and the P+ drain region of the PMOS floating gate transistor while the p-well region is grounded.

9. The single-poly non-volatile memory device of claim 1 , where charge on the p-type floating gate layer is erased using tunneling by grounding the p-well region while applying a first relatively high voltage to the shared n-well region, the P+ source region of the PMOS select transistor, and the P+ drain region of the PMOS floating gate transistor and applying a second voltage to the select gate, where the second voltage is up to one Vdd voltage lower than the first relatively high voltage.

10. The single-poly non-volatile memory device of claim 1 , where the P+ drain region of the PMOS floating gate transistor is connected in common with P+ drain regions from other PMOS floating gate transistors in a common drain NOR array.

11. The single-poly non-volatile memory device of claim 1 , where the P+ source region of the PMOS select transistor is connected in common with P+ source regions from other PMOS select transistors in a common source NOR array.

12. The single-poly non-volatile memory device of claim 1 , where the select gate of the PMOS select transistor is drawn on a source side of the PMOS floating gate transistor.

13. The single-poly non-volatile memory device of claim 1 , where the select gate of the PMOS select transistor is drawn on a drain side of the PMOS floating gate transistor.

14. A single-poly non-volatile memory device, comprising:

a floating gate transistor of a first predetermined conductivity type, where the floating gate transistor comprises a floating gate formed over a floating gate dielectric layer from a first part of a floating gate layer, and source and drain regions formed adjacent to the floating gate in a first well region;

a select transistor serially connected to the floating gate transistor, where the select transistor comprises a select gate formed over a select gate dielectric layer, and source and drain regions formed adjacent to the select gate in the first well region; and

a coupling capacitor formed over a second well region that is isolated from the first well region, comprising a first capacitor plate formed with a second part of the floating gate layer so as to be connected to the floating gate transistor, a capacitor dielectric layer, and a second capacitor plate formed with an underlying portion of the second well region.

15. The single-poly non-volatile memory device of claim 14 , where the select transistor and floating gate transistor each comprise a PMOS transistor formed in the first well region that is an n-well region.

16. The single-poly non-volatile memory device of claim 14 , where the select transistor and floating gate transistor each comprise an NMOS transistor formed in the first well region that is a shared p-well region.

17. The single-poly non-volatile memory device of claim 14 , where the floating gate layer comprises a p-type floating gate layer, and where the coupling capacitor is formed over a p-well region of an underlying substrate and comprises a first capacitor plate formed with a second part of the p-type floating gate layer, a capacitor dielectric layer, and a second capacitor plate formed with an underlying portion of the p-well region.

18. The single-poly non-volatile memory device of claim 14 , where the coupling capacitor is formed over an n-well region of an underlying substrate and comprises a first capacitor plate formed with a second part of the floating gate layer, a capacitor dielectric layer, and a second capacitor plate formed with an underlying portion of the n-well region.

19. The single-poly non-volatile memory device of claim 14 , where the coupling capacitor is formed over the second well region of the first predetermined conductivity, and where the second well region is electrically isolated from the first well region by an underlying semiconductor layer of a second predetermined conductivity type that is opposite to the first predetermined conductivity type.

20. A method for forming a single-poly non-volatile memory device, comprising:

providing a semiconductor substrate structure;

forming a shared n-well region in the semiconductor substrate structure;

forming a p-well region in the semiconductor substrate structure that is isolated from the shared n-well region;

forming one or more dielectric layers over the semiconductor substrate structure to cover at least part of the shared n-well region and p-well region;

forming a polysilicon layer over the one or more dielectric layers which is doped p-type during or after forming the polysilicon layer;

patterning and etching the polysilicon layer to define a PMOS select gate and a PMOS floating gate over the shared n-well region, and to define a first coupling capacitor plate over the p-well region, where the PMOS floating gate and coupling capacitor plate are formed from a single continuous polysilicon conductor that extends from the shared n-well region to cover at least part of the p-well region, thereby defining a second coupling capacitor plate in a portion of the p-well region underlying the polysilicon conductor; and

forming a PMOS select transistor and PMOS floating gate transistor in the shared n-well region by implanting P+ source and drain regions in the shared n-well region of the semiconductor substrate structure substantially adjacent to the PMOS select gate and PMOS floating gate, such that the PMOS select transistor is serially connected to the PMOS floating gate transistor through a shared source or drain region, and the PMOS floating gate is directly connected through the continuous polysilicon conductor to the first coupling capacitor plate.

Assignments (22)