IP Library Granted Patent US 8,987,092
Granted Patent B2
US 8,987,092 · App. 12/110,974 · Granted Mar 24, 2015

Methods for fabricating memory cells having fin structures with semicircular top surfaces and rounded top corners and edges

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Quick Facts
Patent No.
US 8,987,092
App. No.
12/110,974
Granted
Mar 24, 2015
Kind
B2
Abstract

Methods for fabricating a FIN structure with a semicircular top surface and rounded top surface corners and edges are disclosed. As a part of a disclosed method, a FIN structure is formed in a semiconductor substrate. The FIN structure includes a top surface having corners and edges. The FIN structure is annealed where the annealing causes the top surface to have a semicircular shape and the top surface corners and edges to be rounded.

Claims (31)

1. A method for forming a FIN structure with semicircular top surface and rounded top surface corners and edges, comprising:

forming a FIN structure in a semiconductor substrate wherein said FIN structure includes a top surface having corners and edges; and

annealing said FIN structure to effect an initiation and completion of rounding for said method of said top surface corners and edges in a single annealing operation free of any preceding, intermediate and subsequent rounding operations that round said top surface corners and edges in part wherein said single annealing operation causes the top surface area between said corners and edges to have a semicircular shape along the entire surface between anterior and posterior portions of said FIN in a direction orthogonal to the direction between said edges wherein said annealing comprises initially performing a dilute hydrofluoric acid (DHF) clean, and subsequently performing simultaneously both an ammonia/peroxide mix (APM) clean and hydrochloric/peroxide mix (HPM) clean to form native oxide and a H2 anneal.

2. The method of claim 1 wherein said FIN structure is associated with the fabrication of an individual charge storage cell.

3. The method of claim 1 wherein said FIN structure is fabricated from a semiconductor wafer.

4. The method of claim 1 wherein said annealing is performed at a temperature of 650 to 1100 degrees Celsius.

5. The method of claim 1 wherein said annealing is performed at a pressure of 0.1 Torr to 100 Ton.

6. The method of claim 1 wherein said annealing is performed using an H2 flow of 50 sccm to 20 slm.

7. The method of claim 1 wherein said annealing time is 2 seconds to 600 seconds.

8. A method for forming a storage element, comprising:

forming a FIN structure on a semiconductor substrate wherein said forming said FIN structure comprises:

forming a semiconductor FIN structure wherein said semiconductor FIN structure includes a top surface having corners and edges; and

annealing said semiconductor FIN structure to effect the initiation and completion of rounding of said top surface corners and edges for said method in a single annealing operation free of preceding, intermediate and subsequent rounding operations that round said top surface corners and edges in part wherein said single annealing operation causes the top surface area between said corners and edges to have a semicircular shape along the entire surface between anterior and posterior portions of said FIN in a direction orthogonal to the direction between said edges wherein said annealing comprises initially performing a dilute hydrofluoric acid (DHF) clean, and subsequently performing simultaneously both an ammonia/peroxide mix (APM) clean and hydrochloric/peroxide mix (HPM) clean to form native oxide and a H2 anneal, forming a first oxide layer on said semiconductor FIN structure;

forming a charge storage layer on said first oxide layer;

forming a second oxide layer on said charge storage layer; and

forming a polysilicon gate layer on said second oxide layer.

9. The method of claim 8 wherein each of said FIN structures are associated with the fabrication of an individual charge storage cell.

10. The method of claim 8 wherein said FIN structure is formed from a semiconductor wafer.

11. The method of claim 8 wherein said annealing is performed at a temperature of 650 to 1100 degrees Celsius.

12. The method of claim 8 wherein said annealing is performed at a pressure of 0.1 Torr to 100 Ton.

13. The method of claim 8 wherein said annealing is performed using an H2 flow of 50 sccm to 20 slm.

14. The method of claim 8 wherein said annealing time is 2 seconds to 600 seconds.

15. A method for forming a memory array comprising:

forming a semiconductor substrate; and

forming a plurality of storage elements on said semiconductor substrate, comprising:

forming a plurality of semiconductor FIN structures wherein said plurality of semiconductor FIN structures include a top surface having corners and edges; and

annealing the plurality of semiconductor FIN structures to effect the initiation and completion of rounding of said top surface corners and edges for said method in a single annealing operation free of preceding, intermediate and subsequent rounding operations that round said top surface corners and edges in part wherein said single annealing operation causes the top surface area between said corners and edges to have a semicircular shape along the entire surface between anterior and posterior portions of said FIN in a direction orthogonal to the direction between said edges wherein said annealing comprises initially performing in a dilute hydrofluoric acid (DHF) clean, and subsequently performing simultaneously both an ammonia/peroxide mix (APM) clean and hydrochloric/peroxide mix (HPM) clean to form native oxide and a H2 anneal,

forming a first oxide layer on said plurality of semiconductor FIN structures;

forming a charge storage layer on said first oxide layer; and

forming a second oxide layer on the charge storage layer.

16. The method of claim 15 wherein each of said FIN structures are associated with the fabrication of an individual charge storage cell.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
RELEASE OF SECURITY INTEREST Recorded Jun 22, 2018
From: MORGAN STANLEY SENIOR FUNDING INC.,
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 046175/0969 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 22, 2018
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 046173/0955 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 11, 2015
From: SPANSION LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 035891/0086 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 28, 2008
From: KANG, INKUK; XUE, GANG; FANG, SHENQING; SUGINO, RINJI; MA, YI
To: SPANSION, LLC
Reel/Frame 020868/0250 →