Integrated circuit semiconductor device with overlay key and alignment key and method of fabricating the same

1. An integrated circuit semiconductor device comprising:

a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern;

an overlay key region formed in a second portion of the silicon substrate, the overlay key region including a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern by correcting overlay and alignment errors using the second insulating pattern; and

an alignment key region formed in a third portion of the silicon substrate, the alignment key region including a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench.

2. The device of claim 1 , wherein each of the first insulating pattern and the second insulating pattern is formed of a material selected from a group consisting of SiO 2 , SiON, Si 3 N 4 and any combination thereof.

3. The device of claim 1 , wherein each of the first insulating pattern and the second insulating pattern is formed of a triple layer of SiO 2 , Si 3 N 4 , and SiO 2 .

4. The device of claim 1 , wherein each of the first insulating pattern and the second insulating pattern is formed to a thickness of about 100 Å to about 300 Å.

5. The device of claim 1 , wherein each of the first conductive pattern, the second conductive pattern, and the third conductive pattern is formed of a doped polysilicon layer.

6. An integrated circuit semiconductor device comprising:

a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern;

an overlay key region formed in a second portion of the silicon substrate, the overlay key region including a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern by correcting overlay and alignment errors using the second insulating pattern; and

an alignment key region formed in a third portion of the silicon substrate, the alignment key region including a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer filled in the third trench, and a third conductive pattern formed over the second buried insulating layer and the silicon substrate.

7. The device of claim 6 , wherein each of the first insulating pattern and the second insulating pattern is formed of a material selected from a group consisting of SiO 2 , SiON, and Si 3 N 4 or any combination thereof.

8. The device of claim 6 , wherein each of the first insulating pattern and the second insulating pattern is formed to a thickness of about 100 Å to about 300 Å.

9. The device of claim 6 , wherein each of the first conductive pattern, the second conductive pattern, and the third conductive pattern is formed of a doped polysilicon layer.