Semiconductor memory device and manufacturing method thereof

1. A semiconductor memory device comprising:

a supporting substrate;

a semiconductor layer provided above the supporting substrate, and extending in a first direction;

a source layer provided in the semiconductor layer;

a drain layer provided in the semiconductor layer;

a body provided between the source layer and the drain layer in the semiconductor layer, the body being in an electrically floating state, electric charges being accumulated in or emitted from the body to store data;

a bit line connected to the drain layer, and extending in the first direction;

a first gate dielectric film provided on a first side surface of the body;

a first gate electrode provided on the first side surface of the body via the first gate dielectric film;

a first gate line extending in the first direction, connected to a bottom of the first gate electrode, and formed integrally with the first gate electrode using same material;

a second gate dielectric film provided on a second side surface of the body, the second side surface being opposite to the first side surface;

a second gate electrode provided on the second side surface of the body via the second gate dielectric film, the second gate electrode extending upward above a top surface of the body and isolated from the first gate electrode; and

a second gate line extending above the body in a second direction crossing the first direction, connected to an upper portion of the second gate electrode, and formed integrally with the second gate electrode using same material.

2. The semiconductor memory device according to claim 1 , wherein

a plurality of semiconductor layers are provided,

first side surfaces of the semiconductor layers are opposed to each other in a first trench between the adjacent semiconductor layers,

second side surfaces of the semiconductor layers are opposed to each other in a second trench between the adjacent semiconductor layers, and

a plurality of first trenches and a plurality of second trenches are alternately arranged in the second direction.

3. The semiconductor memory device according to claim 1 , wherein a width of a bottom of the body in the first direction is larger than a width of a top surface of the body in the first direction.

4. The semiconductor memory device according to claim 1 , wherein a top surface of the first gate line is located at a lower position than a position of a bottom of the drain layer.

5. A semiconductor memory device comprising:

a supporting substrate;

a semiconductor layer provided above the supporting substrate, and extending in a first direction;

a source layer provided in the semiconductor layer;

a drain layer provided in the semiconductor layer;

a body provided between the source layer and the drain layer in the semiconductor layer, the body being in an electrically floating state, electric charges being accumulated in or emitted from the body to store data;

a bit line connected to the drain layer, and extending in the first direction;

a first gate dielectric film provided on a first side surface of the body;

a first gate electrode provided on the first side surface of the body via the first gate dielectric film and connected to the supporting substrate;

a second gate dielectric film provided on a second side surface of the body, the second side surface being opposite to the first side surface;

a second gate electrode provided on the second side surface of the body via the second gate dielectric film, the second gate electrode extending upward above a top surface of the body and isolated from the first gate electrode; and

a second gate line extending above the body in a second direction crossing the first direction, connected to an upper portion of the second gate electrode, and formed integrally with the second gate electrode using same material.

6. The semiconductor memory device according to claim 5 , wherein

a plurality of semiconductor layers are provided,

first side surfaces of the semiconductor layers are opposed to each other in a first trench between the adjacent semiconductor layers,

second side surfaces of the semiconductor layers are opposed to each other in a second trench between the adjacent semiconductor layers, and

a plurality of first trenches and a plurality of second trenches are alternately arranged in the second direction.

7. The semiconductor memory device according to claim 5 , wherein a width of a bottom of the body in the first direction is larger than a width of a top surface of the body in the first direction.

8. The semiconductor memory device according to claim 6 , wherein the first gate electrode is shared between first surfaces of the semiconductor layers opposed to each other in each of the first trenches.

9. The semiconductor memory device according to claim 5 , wherein a width of an upper portion of the second gate electrode in the first direction is smaller than a width of a lower portion of the second gate electrode in the first direction.

10. A semiconductor memory device comprising:

a supporting substrate;

a semiconductor layer provided above the supporting substrate, and extending in a first direction;

a source layer provided in the semiconductor layer;

a drain layer provided in the semiconductor layer;

a body provided between the source layer and the drain layer in the semiconductor layer, the body being in an electrically floating state, electric charges being accumulated in or emitted from the body to store data;

a bit line connected to the drain layer, and extending in the first direction;

a first gate dielectric film provided on a first side surface of the body;

a first gate electrode provided on the first side surface of the body via the first gate dielectric film and including a first part and a second part;

a second gate dielectric film provided on a second side surface of the body, the second side surface being opposite to the first side surface;

a second gate electrode provided on the second side surface of the body via the second gate dielectric film, the second gate electrode extending upward above a top surface of the body and isolated from the first gate electrode; and

a second gate line extending above the body in a second direction crossing the first direction, connected to an upper portion of the second gate electrode, and formed integrally with the second gate electrode using same material, wherein

a first part is provided below the second gate line and includes two side surfaces facing to the first direction, and

a second part includes a top surface located lower than a top surface of the first part.

11. The semiconductor memory device according to claim 10 , wherein

a plurality of semiconductor layers are provided,

first side surfaces of the semiconductor layers are opposed to each other in a first trench between the adjacent semiconductor layers,

second side surfaces of the semiconductor layers are opposed to each other in a second trench between the adjacent semiconductor layers, and

a plurality of first trenches and a plurality of second trenches are alternately arranged in the second direction.

12. The semiconductor memory device according to claim 10 , wherein a width of a bottom of the body in the first direction is larger than a width of a top surface of the body in the first direction.