Method for designing mask including forming a mesh dummy pattern
View Patent ↗A method for designing a mask is disclosed. A chip region can be defined and reduced to form a parent dummy pattern. A mesh dummy pattern can be formed, and portions where the parent dummy pattern and the mesh dummy pattern overlap each other can be removed to form offspring dummy patterns.
1. A method for designing a mask, comprising:
defining a chip region using a computer;
forming a parent dummy pattern on a portion of the chip region;
forming a mesh dummy pattern on the parent dummy pattern; and
forming offspring dummy patterns by removing portions of the parent dummy pattern and portions of the mesh dummy pattern where they overlap each other,
wherein forming the mesh dummy pattern comprises:
forming first lines having a first width and second lines having a second width on the parent dummy pattern such that the first lines are approximately parallel to the second lines; and
forming third lines having a third width and fourth lines having a fourth width on the parent dummy pattern such that the third lines are approximately parallel to the fourth lines and approximately perpendicular to the first lines,
wherein the first width is different from the second width.
2. The method according to claim 1 , wherein the third width is different from the fourth width.
3. The method according to claim 1 , wherein the third width is the same as the first width, and wherein the fourth width is the same as the second width.
4. The method according to claim 1 , wherein the offspring dummy patterns comprise regular square patterns.
5. The method according to claim 1 , wherein the offspring dummy patterns comprise:
a first group of offspring dummy patterns comprising a plurality of first offspring dummy patterns separated from each other by a distance of the first width; and
a second group of offspring dummy patterns comprising a plurality of second offspring dummy patterns separated from the first group of offspring dummy patterns by a distance of the second width.
6. The method according to claim 1 , wherein the offspring dummy patterns comprise active layer dummy patterns.
7. The method according to claim 1 , further comprising:
forming a main pattern inside the chip region;
forming a dummy pattern prohibition region using the main pattern as a reference; and
removing offspring dummy patterns that are in contact with the dummy pattern prohibition region.
8. The method according to claim 7 , wherein the forming of the main pattern and the forming of the dummy pattern prohibition region are performed before the forming of the parent dummy pattern.
9. The method according to claim 7 , wherein the forming of the main pattern and the forming of the dummy pattern prohibition region are performed after the forming of the parent dummy pattern.