Programmable logic based latches and shift registers

1. A shift register, comprising:

a first latch having a data input within a first logic block (LB), the first LB having a first logic element (LE) comprising an input and an output;

a second latch having a data input;

a first programmable interconnect configured to couple the first latch output to the first LE input;

a second programmable interconnect configured to couple the first LE output to second latch data input; and

a third programmable interconnect configured to decouple the first LE output to the first latch data input.

2. The shift register of claim 1 , wherein the second latch is within a second logic block (LB).

3. The shift register of claim 1 , wherein the interconnect comprises a buffer.

4. The shift register of claim 1 , wherein the interconnect comprises a multiplexer.

5. The shift register of claim 1 , wherein the LB and the programmable interconnects are configured by a configuration circuit.

6. The shift register of claim 1 , wherein the first LB further comprises an output pin for a logic signal generated within the LB to couple to one or more global routing wires, wherein the programmable interconnects is not coupled to the output pin.

7. The shift register of claim 1 , wherein the first LB further comprises a second LE having an input and an output, wherein the data input is coupled to the second LE input, and the second LE output is coupled to the first latch data input.

8. The shift register of claim 1 , wherein the second latch is in a second LB, the second LB further comprising a first LE and a second LE, each LE comprising an input and an output, wherein the second interconnect is coupled to the second LE input in the second LB, and the second LE output of the second LB is coupled to the second latch.

9. The shift register of claim 1 , wherein the second interconnect provides a local signal path between the first and second LB.

10. A method for providing a shift register, comprising:

providing a first latch within a first logic block (LB), the latch having an input;

providing a second latch having an input;

providing a logic element (LE) within the first LB, the LE having an input and an output, the LE output capable of coupling to the first and second latch inputs;

coupling the first latch output to the LE input;

coupling the LE output to the second latch input; and

decoupling the LE output to the first latch input.

11. The method of claim 10 , comprising providing the second latch within a second LB.

12. The method of claim 10 , wherein a buffer is used to couple the first latch output to the LE input.

13. The method of claim 10 , wherein a multiplexer is used to couple the first latch output to the LE input.

14. The method of claim 10 , wherein the interconnect to couple LE output to said first and second latches comprises dedicated local routing wires.

15. The method of claim 10 , wherein the output of LE within first LB is coupled to the second latch via an LE located within the second LB.

16. The method of claim 10 , comprising forming an n-bit shift register by coupling n-latches, wherein each latch output is coupled to next latch with an LE located in the same LB as the latch.

17. The method of claim 10 , wherein the latches are positioned adjacent each other.

18. The method of claim 10 , wherein the latches are vertically adjacent each other.

19. A programmable logic device adapted to implement a shift register, the device comprising:

a logic block comprising:

a latch having an input;

a logic element having an output capable of coupling to an adjacent logic block and the latch input, wherein the output is coupled to the adjacent logic block and decoupled from the latch input; and

an interconnect coupled to the latch and adapted to transmit the latch output to an input of the logic element.

20. The device of claim 19 , wherein the logic element is configured as a route through for the latch output to couple to an adjacent logic block.