Video encoding and video/audio/data multiplexing device
View Patent ↗The present invention provides a buffer architecture and latency reduction mechanism for buffering uncompressed/compressed information. This combination provides for a proficient division of the encoding task and quicker through-put time. The invention teaches a single chip digital signal processing device for real time video/audio compression comprising a plurality of processors, including a video input processor, a motion estimation processor, a digital signal processor, and a bitstream processor, wherein processing and transfer of the signals within the device is done in a macroblock-by-macroblock manner. The device can include a multiplexing processor that is comprised of a storage unit which buffers a compressed video bitstream and a processor which retrieves the compressed video bitstream from the storage unit and produces a multiplexed data stream whereby the compressed video bitstream is processed in a pipeline manner.
1. A single chip digital signal processing device for real time video/audio compression, said device comprising:
a motion estimation processor which receives video data and produces a motion analysis therefrom;
a digital signal processor which, according to said motion analysis, compresses video data that has been processed by the video input processor; and
a bitstream processor which formats video data that has been compressed by the digital signal processor to produce a video bitstream;
wherein said motion estimation processor operates on macroblock a of frame I, said digital signal processor operates on macroblock b of frame I, and said bitstream processor operates on macroblock c of frame I concurrently, wherein a≧b≧c.
2. The single chip digital signal processing device of claim 1 , further comprising a video input processor which receives, analyzes, scales and processes video data, and provides processed video data to the motion estimation processor.
3. The single chip digital signal processing device of claim 2 , further comprising a memory controller connected to and controlling said plurality of processors, wherein said memory controller controls data communication among said digital signal processor, said motion estimation processor, said video input processor and an external storage unit.
4. The single chip digital signal processing device of claim 1 , further comprising a multiplexing processor which multiplexes a plurality of digital signals of said video bitstream with a second bitstream to produce a multiplexed data stream.
5. The single chip digital signal processing device of claim 4 , further comprising a global controller which controls and schedules said video input processor, said motion estimation processor, said digital signal processor, said bitstream processor, said multiplexing processor and said memory controller.
6. The single chip digital signal processing device of claim 4 wherein said motion estimation processor, said digital signal processor, said video input processor, said bitstream processor and said multiplexing processor operate in parallel.
7. The single chip digital signal processing device of claim 4 , wherein said second bitstream comprises at least one of an audio bitstream and a user data bitstream.