Method of forming U-shaped floating gate with a poly meta-stable polysilicon layer

1. A method of manufacturing a semiconductor device comprising:

forming a tunnel oxide layer in an active region of a semiconductor substrate;

forming a poly floating gate on the tunnel oxide layer;

forming a photoresist layer on an entire surface of the semiconductor substrate;

selectively patterning the photoresist layer to form photoresist patterns partially exposing the poly floating gate;

forming side floating gates on the photoresist patterns and the partially exposed floating gate;

forming a U-shaped floating gate by removing the photoresist patterns and the side floating gates formed only on the photoresist patterns;

forming a poly meta-stable polysilicon layer on the U-shaped floating gate; and

forming a control gate on the entire surface of the semiconductor substrate including the meta-stable poly silicon layer.

2. The method of claim 1 , wherein the poly meta-stable polysilicon layer is particle-shaped.

3. The method of claim 2 , wherein the poly meta-stable poly silicon layer is formed by performing a meta-stable polysilicon annealing process at a predetermined temperature in an N 2 atmosphere.

4. The method of claim 3 , wherein the predetermined temperature is between 800° C. and 1,500° C.

5. The method of claim 1 , wherein the U-shaped floating gate is formed by a photoresist ashing process using a lift-off method.

6. The method of claim 1 , wherein, the photoresist is formed to a thickness between 1,000 Å and 2,000 Å.

7. The method of claim 1 , further comprising, after forming the poly meta-stable polysilicon layer and before forming the control gate:

forming a dielectric layer over the poly meta-stable poly silicon layer.

8. A method of manufacturing a semiconductor device comprising:

forming a tunnel oxide layer on an active region of a semiconductor substrate;

forming a first floating gate on and contacting the tunnel oxide layer;

forming second and third floating gates on and contacting the first floating gate, wherein the second and third floating gates extend perpendicular to the first floating gate;

forming a poly meta-stable polysilicon layer on the first, second and third floating gates; and

forming a control gate on the semiconductor substrate including the poly meta-stable polysilicon layer,

wherein the forming the second and third floating gates comprises:

forming a photoresist layer on the semiconductor substrate including the first floating gate;

forming photoresist patterns partially exposing the first floating gate by selectively patterning the photoresist layer;

forming side floating gates on the photoresist patterns and the partially exposed first floating gate;

removing the photoresist patterns and the side floating gates formed only on the photoresist patterns.

9. The method of claim 8 , wherein the photoresist layer is formed at a thickness of between 1,000 Å and 2,000 Å.

10. The method of claim 8 , wherein forming the poly meta-stable polysilicon layer comprises:

performing a meta-stable polysilicon annealing process on the first, second and third floating gates in a N2 atmosphere at a predetermined temperature.

11. The method of claim 10 , wherein the predetermined temperature is between 800° C. and 1,500° C.

12. The method of claim 8 , further comprising, after forming the poly meta-stable polysilicon layer and before forming the control gate:

forming a dielectric layer over the poly meta-stable polysilicon layer.

13. The method of claim 12 , wherein the dielectric layer comprises an ONO layer.