Systems and methods for providing defect-tolerant logic devices
View Patent ↗The present invention describes systems and methods to provide defect-tolerant logic devices. An exemplary embodiment of the present invention provides a defect-tolerant logic device including a plurality of CMOS gates and at least one defective CMOS gate included within the plurality of CMOS gates. Additionally, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-NMOS transistor if a P-network of the at least one defective CMOS gate is diagnosed as defective. Furthermore, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-PMOS transistor if the N-network of the at least one defective CMOS gate is diagnosed as defective.
1. A defect-tolerant logic device comprising:
a plurality of CMOS gates;
at least one defective CMOS gate included within the plurality of CMOS gates;
wherein the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-NMOS transistor if a P-network of the at least one defective CMOS gate is diagnosed as defective; and
wherein the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-PMOS transistor if the N-network of the at least one defective CMOS gate is diagnosed as defective.
2. The defect-tolerant logic device of claim 1 , wherein the P-network of the at least one defective CMOS gate is enabled to be reconfigured into a pull-up transistor if the P-network is diagnosed as defective.
3. The defect-tolerant logic device of claim 1 , wherein the N-network of the at least one defective CMOS gate is enabled to be reconfigured into a pull-down transistor if the N-network is diagnosed as defective.
4. The defect-tolerant logic device of claim 1 , further comprising a plurality of reconfiguration traces in communication with the plurality of CMOS gates.
5. The defect-tolerant logic device of claim 4 , wherein the at least one defective CMOS gate further is enabled to receive a reconfiguration control signal transmitted over the plurality of reconfiguration traces.
6. The defect-tolerant logic device of claim 5 , wherein the reconfiguration control signal includes data corresponding to the location of the at least one defective CMOS gate.
7. The defect-tolerant logic device of claim 5 , wherein the reconfiguration control signal includes data indicating whether the P-network or the N-network of the at least one defective CMOS gate is defective.
8. The defect-tolerant logic device of claim 1 , wherein the at least one defective CMOS gate is enabled to be reconfigured from operation as a pseudo-PMOS transistor to normal operation.
9. The defect-tolerant logic device of claim 1 , wherein the at least one defective CMOS gate is enabled to be reconfigured from operation as a pseudo-NMOS transistor to normal operation.
10. A method for correcting a defective logic device, the method comprising:
receiving a diagnosis of at least one defective CMOS gate among a plurality of CMOS gates of a logic device;
reconfiguring the at least one defective CMOS gate to a pseudo-NMOS transistor if a P-network of the at least one defective CMOS gate is diagnosed as defective; and
reconfiguring the at least one defective CMOS gate to a pseudo-PMOS transistor if the N-network of the at least one defective CMOS gate is diagnosed as defective.
11. The method for correcting a defective logic device of claim 10 , wherein the step of reconfiguring the at least one defective CMOS gate to a pseudo-NMOS transistor includes converting the P-network into a pull-up transistor.
12. The method for correcting a defective logic device of claim 10 , wherein the step of reconfiguring the at least one defective CMOS gate to a pseudo-PMOS transistor includes converting the N-network into a pull-down transistor.
13. The method for correcting a defective logic device of claim 10 , further comprising the step of providing a plurality of reconfiguration traces in communication with the plurality of CMOS gates.
14. The method for correcting a defective logic device of claim 13 , further comprising the steps of transmitting a reconfiguration control signal over the plurality of reconfiguration traces and receiving the reconfiguration control signal at the at least one defective CMOS gate.
15. The method for correcting a defective logic device of claim 14 , wherein the reconfiguration control signal includes data corresponding to the location of the at least one defective CMOS gate.
16. The method for correcting a defective logic device of claim 14 , wherein the reconfiguration control signal includes data indicating whether the P-network or the N-network of the at least one defective CMOS gate is defective.
17. The method for correcting a defective logic device of claim 10 , further comprising the step of reconfiguring the at least one defective CMOS gate from operation as a pseudo-PMOS transistor to normal operation.
18. The method for correcting a defective logic device of claim 10 , further comprising the step of reconfiguring the at least one defective CMOS gate from operation as a pseudo-NMOS transistor to normal operation.
19. A method increasing yield in logic device manufacturing, the method comprising:
fabricating a plurality of logic devices;
diagnosing at least one defective logic device from the plurality of logic devices;
diagnosing at least one defective CMOS gate in the at least one defective logic device;
reconfiguring the at least one defective CMOS gate to an pseudo-NMOS transistor if a P-network of the at least one defective CMOS gate is diagnosed as defective; and
reconfiguring the at least one defective CMOS gate to a pseudo-PMOS transistor if the N-network of the at least one defective CMOS gate is diagnosed as defective.
20. The method of increasing yield in logic device manufacturing of claim 19 , wherein the reconfiguring steps are repeated until the yield reaches an predetermined percentage of the total number of logic devices fabricated.