IP Library Granted Patent US 7,687,849
Granted Patent B2
US 7,687,849 · App. 12/128,796 · Granted Mar 30, 2010

Method for manufacturing semiconductor integrated circuit device

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Quick Facts
Patent No.
US 7,687,849
App. No.
12/128,796
Granted
Mar 30, 2010
Kind
B2
Abstract

Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.

Claims (27)

1. A semiconductor device comprising:

a semiconductor substrate having a main surface;

a first insulating film formed on the main surface of the semiconductor substrate;

a silicon film formed on the first insulating film, which has a first sidewall positioned adjacent to the first insulating film and a second sidewall positioned apart from the first insulating film;

a refractory metal film formed above the silicon film and having a third sidewall;

a second insulating film formed on the second and third sidewalls; and

a third insulating film formed on the first sidewall, wherein a lower edge of the second insulating film is located not less than 10 nanometers below an upper edge of the silicon film.

2. The device of claim 1 , further comprising a barrier layer inserted between the silicon film and the refractory metal film.

3. The device of claim 2 , wherein the barrier layer is formed to prevent the polysilicon layer from forming a silicide layer with the refractory metal.

4. The device of claim 2 , wherein the barrier layer comprises nitride of a metal.

5. The device of claim 2 , wherein the barrier layer comprises a tungsten nitride.

6. The device of claim 1 , wherein the refractory metal is made of tungsten.

7. The device of claim 1 , wherein the lower edge of the second insulating film is located not more than 40 nanometers below an upper edge of the silicon film.

8. The device of claim 1 , wherein the second insulating film comprises a silicon nitride film and the third insulating film comprises a silicon oxide film.

9. A semiconductor device having a multilayer gate structure for a field effect transistor device, the field effect transistor device having an active region formed within a semiconductor substrate beneath a gate dielectric covering a substrate surface of the semiconductor substrate, the gate stack structure comprising:

a polysilicon layer formed on the gate dielectric;

a metal layer;

a barrier layer formed between the polysilicon layer and the metal layer;

a first dielectric passivation liner covering upper sidewall portions of the gate stack structure above a liner edge; and

a second dielectric sidewall liner covering a lower sidewall portion below the liner edge;

wherein the liner edge is located not less than 10 nanometers below an upper edge of the polysilicon layer.

10. The device of claim 9 , wherein the barrier layer is formed to prevent the polysilicon layer from forming a silicide layer with the metal layer.

11. The device of claim 10 , wherein the barrier layer comprises nitride of a metal.

12. The device of claim 11 , wherein the metal layer comprises a refractory metal.

13. The device of claim 12 , wherein the refractory metal is tungsten.

14. The device of claim 9 , wherein the liner is located not more than 40 nanometers below an upper edge of the polysilicon film.

15. The device of claim 9 , wherein the first dielectric sidewall liner comprises a silicon oxide film and the second dielectric sidewall liner comprises a silicon nitride film.

Assignments (2)
LICENSE Recorded Nov 8, 2011
From: SEMICONDUCTOR PATENT CORPORATION
To: SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 027193/0103 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 19, 2011
From: ELPIDA MEMORY, INC.
To: SEMICONDUCTOR PATENT CORPORATION
Reel/Frame 026779/0204 →