Methods of Fabricating Transistors and Structures Thereof

1 . A method of fabricating a transistor, the method comprising:

forming a gate dielectric over a workpiece;

forming a gate over the gate dielectric; and

forming sidewall spacers over the gate dielectric and the gate, the sidewall spacers comprising germanium oxide (GeO or GeO 2 ).

2 . The method according to claim 1 , further comprising removing the sidewall spacers.

3 . The method according to claim 2 , wherein removing the sidewall spacers comprises using deionized water, an aqueous solvent, water, a dilute acidic solution, or a dilute basic solution.

4 . The method according to claim 1 , further comprising altering at least a source or drain region in the workpiece proximate the sidewall spacers.

5 . The method according to claim 4 , wherein altering the at least a source or drain region comprises forming a silicide.

6 . The method according to claim 4 , wherein altering at least the source or drain region comprises implanting at least one dopant into a workpiece proximate the sidewall spacers.

7 . The method according to claim 6 , further comprising annealing the semiconductor wafer, causing dopants of the doped semiconductive material of the workpiece to diffuse into the semiconductor wafer.

8 . A method of manufacturing a semiconductor device, the method comprising:

providing a workpiece;

forming a gate dielectric over the workpiece;

forming a gate over the gate dielectric;

forming sidewall spacers over the gate dielectric and the gate, the sidewall spacers comprising germanium oxide (GeO or GeO 2 ); and

altering the workpiece proximate the sidewall spacers.

9 . The method according to claim 8 , further comprising forming a liner over the gate, the gate dielectric, and the workpiece, before forming the sidewall spacers.

10 . The method according to claim 9 , wherein forming the liner comprises forming a nitride material or an oxide material.

11 . The method according to claim 8 , further comprising removing the sidewall spacers, and forming a stress-inducing material over the gate and gate dielectric.

12 . The method according to claim 8 , wherein forming the sidewall spacers comprises depositing a layer of GeO or GeO 2 over the gate, the gate dielectric, and the workpiece, and anisotropically etching the layer of GeO or GeO 2 .

13 . The method according to claim 12 , wherein anisotropically etching the layer of GeO or GeO 2 comprises using a reactive ion etch (RIE) process.

14 . A semiconductor device manufactured in accordance with claim 8 .

15 . A method of manufacturing a semiconductor device, the method comprising:

providing a workpiece;

forming a gate dielectric material over the workpiece;

forming a gate material over the gate dielectric material;

patterning the gate material and the gate dielectric material to form a plurality of gates and a plurality of gate dielectrics, the plurality of gates and the plurality of gate dielectrics comprising sidewalls;

forming sidewall spacers over the sidewalls of the plurality of gates and the plurality of gate dielectrics, the sidewall spacers comprising germanium oxide (GeO or GeO 2 );

altering the workpiece proximate the sidewall spacers;

removing the sidewall spacers; and

forming a stress-inducing material over the plurality of gates and the plurality of gate dielectrics.

16 . The method according to claim 15 , wherein removing the sidewall spacers comprises rinsing the workpiece with water or deionized water.

17 . The method according to claim 15 , further comprising forming first sidewall spacers on the gate dielectric and the gate, before forming the sidewall spacers over the gate dielectric and the gate, wherein forming the sidewall spacers over the gate dielectric and the gate comprises forming second sidewall spacers over the first sidewall spacers.

18 . The method according to claim 17 , further comprising forming shallow implantation regions in a top surface of the workpiece, after forming the first sidewall spacers, and further comprising forming deep implantation regions in the semiconductive material, after forming the second sidewall spacers.

19 . The method according to claim 16 , wherein patterning the gate material and the gate dielectric material comprises forming at least one first transistor comprising a p channel metal oxide semiconductor (PMOS) field effect transistor (FET) of a CMOS device and forming at least one second transistor comprising an n channel metal oxide semiconductor (NMOS) FET of the CMOS device.

20 . The method according to claim 19 , wherein forming the stress-inducing material comprises forming a first stress-inducing material over the PMOS FET and forming a second stress-inducing material over the NMOS FET, the second stress-inducing material comprising a different material than the first stress-inducing material.

21 . The method according to claim 20 , wherein forming the first stress-inducing material comprises forming a material adapted to introduce a compressive stress to a channel region of the PMOS FET, and wherein forming the second stress-inducing material comprises forming a material adapted to introduce a tensile stress to a channel region of the NMOS FET.

22 . The method according to claim 15 , further comprising, before forming the sidewall spacers comprising germanium oxide:

forming nitride and/or oxide spacers on sidewalls of the plurality of gates and the plurality of gate dielectrics;

implanting at least one dopant into the workpiece proximate the nitride and/or oxide spacers;

annealing the workpiece; and

removing the nitride and/or oxide spacers from the sidewalls of the plurality of gates and the plurality of gate dielectrics.

23 . The method according to claim 22 , wherein annealing the workpiece is before, or after removing the nitride and/or oxide spacers.