Transparent nanowire transistors and methods for fabricating same
View Patent ↗Disclosed are fully transparent nanowire transistors having high field-effect mobilities. The fully transparent nanowire transistors disclosed herein include one or more nanowires, a gate dielectric prepared from a transparent inorganic or organic material, and transparent source, drain, and gate contacts fabricated on a transparent substrate. The fully transparent nanowire transistors disclosed herein also can be mechanically flexible.
1. A nanowire transistor device comprising:
one or more semiconducting nanowires extending between a source electrode and a drain electrode, and
a gate dielectric in contact with the one or more nanowires,
wherein each of the gate dielectric, the source electrode and the drain electrode is transparent, and
wherein the gate dielectric comprises a multi-layer composition, the multi-layer composition comprising periodically alternating layers, wherein the alternating layers comprise one or more layers comprising a polarizable moiety, and one or more layers comprising a silyl or siloxane moiety.
2. A nanowire transistor device comprising:
one or more semiconducting nanowires extending between a source electrode and a drain electrode, and
a gate dielectric in contact with the one or more nanowires,
wherein each of the gate dielectric, the source electrode and the drain electrode is transparent, and
wherein each of the source electrode and the drain electrode independently comprises indium tin oxide, indium zinc oxide, indium oxide, zinc oxide, zinc indium tin oxide, fluorinated tin oxide, gallium zinc oxide, gallium indium oxide, or gallium indium tin oxide.
3. A nanowire transistor device comprising:
one or more semiconducting nanowires extending between a source electrode and a drain electrode, and
a gate dielectric in contact with the one or more nanowires,
wherein each of the gate dielectric, the source electrode and the drain electrode is transparent, and
wherein the transparent gate electrode is defined under the gate dielectric and comprises indium tin oxide, indium zinc oxide, indium oxide, zinc oxide, zinc indium tin oxide, fluorinated tin oxide, gallium zinc oxide, gallium indium oxide, or gallium indium tin oxide.
4. The device of claim 2 , wherein the one or more semiconducting nanowires comprise one or more elements selected from Group 12 , Group 13 , Group 14 , Group 15 and Group 16 .
5. The device of claim 4 , wherein the one or more semiconducting nanowires are selected from p-type Ge nanowires and n-type Ge nanowires.
6. The device of claim 2 , wherein the one or more semiconducting nanowires comprise a transparent metal oxide.
7. The device of claim 6 , wherein the one or more metal oxide nanowires are selected from ZnO nanowires, In 2 O 3 nanowires, and SnO 2 nanowires.
8. The device of claim 2 , wherein the nanowire transistor comprises a single semiconducting nanowire.
9. The device of claim 2 , wherein the nanowire transistor comprises a plurality of semiconducting nanowires.
10. The device of claim 2 , wherein the gate dielectric comprises one or more transparent metal oxides.
11. The device of claim 1 , wherein the polarizable moiety comprises a stilbazonium group.
12. The device of claim 1 , wherein at least some of the alternating layers are coupled to an adjacent layer by a coupling layer comprising a siloxane matrix.
13. The device of claim 12 , wherein at least some of the alternating layers are coupled to one another or the siloxane matrix via a condensation reaction.
14. The device of claim 1 , wherein at least some of the alternating layers comprise a condensation product of a silane-substituted stilbazolium compound and a trisiloxane compound.
15. The device of claim 1 , wherein the alternating layers comprise one or more layers comprising a sigma moiety.
16. The device of claim 15 , wherein at least some of the alternating layers comprise a condensation product of a bis(silyl)-C 4 - about C 10 alkyl compound and a trisiloxane compound.
17. The device of claim 2 , wherein the gate dielectric comprises a crosslinked polymeric material.
18. The device of claim 2 comprising a transparent gate electrode defined under the gate dielectric.
19. The device of claim 2 , wherein the gate dielectric is deposited on a transparent substrate.
20. The device of claim 19 , wherein the transparent substrate is glass or plastic.
21. An array comprising a device of claim 2 .
22. An electronic circuit comprising the array of claim 21 .
23. The device of claim 1 , wherein the one or more semiconducting nanowires are selected from p-type Ge nanowires and n-type Ge nanowires.
24. The device of claim 1 , wherein the one or more semiconducting nanowires are selected from ZnO nanowires, In 2 O 3 nanowires, and SnO 2 nanowires.
25. The device of claim 2 , wherein the gate dielectric comprises a multi-layer composition, the multi-layer composition comprising periodically alternating layers, wherein the alternating layers comprise one or more layers comprising a polarizable moiety, and one or more layers comprising a silyl or siloxane moiety.
26. The device of claim 18 , wherein the transparent gate electrode comprises indium tin oxide, indium zinc oxide, indium oxide, zinc oxide, zinc indium tin oxide, fluorinated tin oxide, gallium zinc oxide, gallium indium oxide, or gallium indium tin oxide.
27. The device of claim 3 , wherein the one or more semiconducting nanowires are selected from p-type Ge nanowires, n-type Ge nanowires, ZnO nanowires, In 2 O 3 nanowires, and SnO 2 nanowires.