Non-volatile memory device

1. A nonvolatile memory device comprising:

a memory cell array including memory cells each having a variable resistance element for nonvolatilely storing data identified by an electrically rewritable resistance value;

a first data latch storing write and erase data to be written on a given group of memory cells of the memory cell array for a write and erase operation;

a second data latch storing reference data for performing a compensation operation of the given group to compensate write and erase disturbance accompanied by the write or erase operation;

wherein the second data latch stores data read from the given group of memory cells, and

wherein the write and erase operations include controlling operations based on prohibition of an additional write and prohibition of an additional erase for a given bit that is identified by a comparison between the data stored in the first data latch and the second data latch.

2. The nonvolatile memory device according to claim 1 , wherein the reference data includes data used for a weak erase or weak write operation performed for compensating unselected memory cells that are affected by the write and erase disturbance when the write or erase operation is performed based on the data stored in the first data latch, and

wherein, after the write or erase operation based on the data stored in the first data latch is performed, the weak erase or weak write operation for compensating the unselected memory cells is performed based on data stored in the second data latch.

3. The nonvolatile memory device according to claim 2 , wherein weak erase voltage applied to the memory cell in the weak erase operation is lower than erase voltage applied to the memory cell in the erase operation, and

wherein time of applying the weak erase voltage to the memory cell in the weak erase operation is longer than time of applying the write voltage when the write operation.

4. The nonvolatile memory device according to claim 2 , wherein weak write voltage applied to the memory cell in the weak write operation is lower than write voltage applied to the memory cell in the write operation, and

wherein time of applying the weak write voltage to the memory cell when the weak write operation is shorter than time of applying the erase voltage in the erase operation.

5. The nonvolatile memory device according to claim 1 , wherein the compensation data includes data used for a weak erase or weak write operation performed for compensating unselected memory cells that are affected by the write and erase disturbance when the write or erase operation is performed based on the data stored in the first data latch, and

wherein, in advance of the write or erase operation based on the data stored in the first data latch is performed, the weak erase or weak write operation for compensating the unselected memory cells is performed based on data stored in the second data latch.

6. The nonvolatile memory device according to claim 5 , wherein weak erase voltage applied to the memory cell in the weak erase operation is lower than erase voltage applied to the memory cell in the erase operation, and

wherein time of applying the weak erase voltage to the memory cell when the weak erase operation is longer than time of applying the write voltage in the write operation.

7. The nonvolatile memory device according to claim 5 , wherein weak write voltage applied to the memory cell in the weak write operation is lower than write voltage applied to the memory cell in the write operation, and

wherein time of applying the weak write voltage to the memory cell when the weak write operation is shorter than time of applying the erase voltage in the erase operation.

8. The nonvolatile memory device according to claim 1 , wherein the memory cell array has row-direction wirings and column-direction wirings that intersect each other, and

wherein the memory cell is configured by stacking a variable resistance element and a rectifying device at each intersection of the row-direction wirings and the column-direction wirings.

9. The nonvolatile memory device according to claim 1 further comprising a state machine configured to apply given voltages to the memory cell,

wherein the state machine performs the write operation, the erase operation, and the compensation operation for write or erase disturbance.

10. The nonvolatile memory device according to claim 9 , wherein the state machine repeatedly performs the write operation, the erase operation, and the compensation operation for write or erase disturbance.

11. A nonvolatile memory device comprising:

a memory cell array including memory cells each having a variable resistance element for nonvolatilely storing data identified by an electrically rewritable resistance value;

a first data latch storing a first write data stored in a part of a given group of memory cells, and

a second data latch storing a second write data read from the given group of memory cells except the part of the given group of the memory cells,

wherein, after the data stored in the given group of the memory cells are collectively erased, the first write data and the second write data are written on each corresponding position of the given group of memory cells.