Semiconductor apparatus and production method of the same
View Patent ↗In order to provide a highly integrated semiconductor apparatus and a production method thereof which can avoid the floating of a channel portion that causes a problem when constituting a memory cell from three-dimensional transistors, a semiconductor apparatus includes: multiple three-dimensional transistors each of which includes: a first pillar; a channel portion provided at the first pillar; diffused layers formed at both an upper portion and a lower portion of the channel portion; and a gate electrode provided around the channel portion via a gate insulation film; and a second pillar which is electrically conductive, wherein the multiple three-dimensional transistors are arranged on a well area while surrounding the second pillar, the multiple three dimensional transistors share the second pillar, and the channel portions of the multiple three dimensional transistors are each connected to the second pillar by a channel connection portion. In addition, six three-dimensional transistors preferably share the second pillar which is a single pillar.
1. A semiconductor apparatus comprising:
a plurality of three-dimensional transistors each of which comprises:
a first pillar;
a channel portion provided at the first pillar;
diffused layers formed at both an upper portion and a lower portion of the channel portion; and
a gate electrode provided around the channel portion via a gate insulation film; and
a second pillar which is electrically conductive, wherein
the plurality of three-dimensional transistors are arranged on a well area while surrounding the second pillar,
the plurality of three dimensional transistors share the second pillar, and
the channel portions of the plurality of three dimensional transistors are each connected to the second pillar by a channel connection portion.
2. A semiconductor apparatus according to claim 1 , wherein six three-dimensional transistors are provided and share the second pillar which is a single pillar, and the six three-dimensional transistors are connected to the second pillar while surrounding the second pillar.
3. A semiconductor apparatus according to claim 2 , wherein
each of the three-dimensional transistors comprises both a lower diffused layer leading portion and a gate electrode leading portion that are close to the first pillar, and
the three-dimensional transistors surrounded by the well layer constitute a module in which each of the three-dimensional transistors is arranged at a vertex of a hexagon that has a center at which the second pillar is set.
4. A semiconductor apparatus according to claim 3 , wherein the module is arranged in a honeycomb state.
5. A semiconductor apparatus production method comprising steps of:
forming a channel portion provided at each of multiple first pillars;
forming diffused layers at an upper portion and a lower portion of the channel portion; forming each of multiple three-dimensional transistors by forming a gate terminal around the channel portion via a gate insulation film; and
arranging the plurality of three-dimensional transistors on a well area while surrounding a second pillar which is electrically conductive, wherein
the multiple three-dimensional transistors share the second pillar which is a single pillar, and
the channel portions of the multiple three dimensional transistors are respectively connected to the second pillar by a channel connection portion.
6. A semiconductor apparatus production method according to claim 5 , wherein six sets of the three-dimensional transistors share the second pillar and are connected to the second pillar while surrounding the second pillar.
7. A semiconductor apparatus production method according to claim 6 , wherein
each of the three-dimensional transistors comprises both a lower diffused layer leading portion and a gate electrode leading portion that are formed to be close to the first pillar, and
each of the three-dimensional transistors is arranged as a module surrounded by the well layer and is arranged at a vertex of a hexagon that has a center at which the second pillar is set.
8. A semiconductor apparatus production method according to claim 7 , wherein the module is arranged in a honeycomb state.
9. A semiconductor apparatus comprising a transistor which comprises:
a first pillar formed in a vertical direction on a substrate;
a first diffused layer formed on the first pillar;
a second diffused layer formed on the first pillar;
a channel portion provided between the first and second diffused layers;
a gate insulation film covering a surface of the channel portion; and
a second pillar formed in a vertical direction on the substrate, wherein
the channel portion of the first pillar is electrically connected to the second pillar.
10. A semiconductor apparatus according to claim 9 , wherein
the first pillar is plural,
the plurality of first pins are arranged around the second pillar, and
each of the channel portions of the plurality of first pillars is electrically connected to the second pillar.
11. A semiconductor apparatus according to claim 10 , wherein the first pillar and the plurality of second pillars constitute one set of pins, and the semiconductor apparatus comprises a plurality of sets of pins.