Phase lock loop semiconductor device

1. A semiconductor device comprising:

a phase locked loop circuit, referred to as PLL circuit, a buffer amplifier, and an output terminal;

an input terminal; and

a comparator between said buffer amplifier and said output terminal;

wherein a control voltage of a voltage controlled oscillator circuit in said PLL circuit is outputted to said output terminal via said buffer amplifier, and

wherein said comparator has one of its input ends connected to an output end of said buffer amplifier, the other input end connected to said input terminal, and its output end connected to said output terminal.

2. The semiconductor device as defined in claim 1 further comprising:

a voltage generating circuit that generates a voltage, which serves as a judging reference for the signal level of a serial data signal;

a switch circuit that performs switching operations so that the output of said buffer amplifier is connected to one of the input ends of said comparator in test mode and an output of said voltage generating circuit is connected to the other input end of said comparator in normal mode; wherein

said input terminal receives said serial data signal.

3. The semiconductor device as defined in claim 1 , further comprising:

a voltage generating circuit that generates a voltage, which serves as a judging reference for the signal level of a serial data signal; and

a switch circuit that performs switching operations so that the output of said buffer amplifier is connected to one of the input ends of said comparator in the test mode, and in the normal mode the output of said voltage generating circuit is connected, via said buffer amplifier, to said one of the input ends of said comparator instead of connecting the input of said buffer amplifier to the output of said voltage controlled oscillator circuit; wherein

said input terminal receives said serial data signal.

4. The semiconductor device as defined in claim 1 wherein said buffer amplifier is externally gain-adjustable.

5. The semiconductor device as defined in claim 4 wherein the gain of said buffer amplifier is fixed in a normal mode and adjustable in a test mode.

6. The semiconductor device as defined in claim 4 wherein the gain of said buffer amplifier is larger in a test mode than in a normal mode.

7. The semiconductor device as defined in claim 1 wherein an input end of said buffer amplifier is connected to a control input terminal of said voltage controlled oscillator circuit.

8. The semiconductor device as defined in claim 7

wherein said PLL circuit comprises a filter circuit having a second capacitance element connected in parallel to a series circuit of a first capacitance element and a resistance element, between the control input terminal of said voltage controlled oscillator circuit and ground, and the input end of said buffer amplifier is connected to one end of said first capacitance element having the other end grounded, instead of the control input terminal of said voltage controlled oscillator circuit.