Wiring structure and semiconductor device, and their fabrication methods
View Patent ↗A fabrication method for a wiring structure of the present invention includes: a process of forming a conductive wiring layer; a process of forming a wiring pattern on the wiring layer; a process of forming an insulative wiring interlayer film between wires of the wiring pattern; and a process of forming a plurality of longitudinal hole-shaped fine pores in the wiring interlayer film in a thickness direction of the wiring interlayer film by etching with a mask including one of nano-particles and material including nano-particles.
1. A fabrication method of a wiring structure, comprising:
forming a wiring pattern over a semiconductor substrate;
forming a first insulating film on the wiring pattern, the first insulating film being filled between wires of the wiring pattern;
forming a mask layer by using a coating interlayer insulating film which includes nano particles;
removing a part of the first insulating film to form a plurality of pores in the first insulating film by using the mask layer as an etching mask;
removing the mask layer; and
forming a second insulating film on the first insulating film to cover the plurality of pores, wherein a plurality of cavities remain in the first insulating film.
2. The fabrication method according to claim 1 , wherein removing the mask layer comprises removing the nano particles from a surface of the first insulating film by dry etching.
3. The fabrication method according to claim 1 , wherein a material of the nano particles is selected from a group of Si, CdSe, ZnS, PbSe and carbon balls.
4. The fabrication method according to claim 1 , wherein a diameter of each of the nano particles is in a range from 4 nm to 30 nm.
5. The fabrication method according to claim 1 , wherein the coating interlayer insulating film includes 0.01% to 50% of the nano particles.
6. The fabrication method according to claim 1 , wherein forming the mask layer comprises:
forming a tungsten layer on the first insulating film;
removing the nano particles from the coating interlayer insulating film by dry etching; and
removing a part of the tungsten layer by using remaining part of the coating interlayer insulating film as an etching mask.
7. The fabrication method according to claim 6 , wherein removing the mask layer comprises removing the tungsten layer from a surface of the first insulating film by dry etching.
8. The fabrication method according to claim 6 , wherein a material of the nano particles is selected from a group of Si, CdSe, ZnS, PbSe and carbon balls.
9. The fabrication method according to claim 6 , wherein a diameter of each of the nano particles is in a range from 4 nm to 30 nm.
10. The fabrication method according to claim 6 , wherein the coating interlayer insulating film includes 0.01% to 50% of the nano particles.
11. The fabrication method according to claim 1 , wherein forming the first insulating film comprises:
forming a SOD film over the wiring pattern by coating method; and flattening a surface of the SOD film by using CMP method.
12. The fabrication method according to claim 1 , wherein the second insulating film is formed on top of the plurality of pores in the first insulating film and the plurality of cavities are formed so that the plurality of pores contain air in their inside.