Post passivation interconnection schemes on top of the IC chips
View Patent ↗A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
1. A chip comprising:
a silicon substrate;
an ESD circuit on said silicon substrate;
an internal circuit on said silicon substrate;
a driver, receiver or I/O circuit on said silicon substrate;
a dielectric layer over said silicon substrate;
a fine-line metallization structure over said silicon substrate and in said dielectric layer, wherein said fine-line metallization structure comprises a first interconnecting structure connected to a first terminal of said driver, receiver or I/O circuit, a second interconnecting structure connected to said internal circuit, and a third interconnecting structure connected to said ESD circuit and to a second terminal of said driver, receiver or I/O circuit, wherein said fine-line metallization structure comprises a copper line and a first adhesion layer at a bottom of said copper line and at a sidewall of said copper line;
a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride layer;
a first via in said passivation layer, wherein said first via is connected to said first interconnecting structure;
a second via in said passivation layer, wherein said second via is connected to said second interconnecting structure; and
a fourth interconnecting structure over said passivation layer, wherein said fourth interconnecting structure is connected to said first and second vias, wherein said first terminal is connected to said internal circuit through, in sequence, said first interconnecting structure, said first via, said fourth interconnecting structure, said second via and said second interconnecting structure, wherein said fourth interconnecting structure comprises a second adhesion layer, a seed layer on said second adhesion layer, and an electroplated metal layer on said seed layer, wherein said electroplated metal layer has a sidewall not covered by said second adhesion layer.
2. The chip of claim 1 , wherein said nitride layer has a thickness greater than 0.3 micrometers.
3. The chip of claim 1 , wherein said nitride layer comprises an oxynitride.
4. The chip of claim 1 , wherein said third interconnecting structure provides an access to an external clock for said ESD circuit and for said second terminal.
5. The chip of claim 1 , wherein said third interconnecting structure provides an access to an external signal for said ESD circuit and for said second terminal.
6. The chip of claim 1 further comprising a polymer layer over said passivation layer, wherein said polymer layer comprises a portion over said fourth interconnecting structure.
7. The chip of claim 1 , wherein said electroplated metal layer comprises copper.
8. The chip of claim 1 , wherein said second adhesion layer comprises titanium.
9. A chip comprising:
a silicon substrate;
an ESD circuit on said silicon substrate;
an internal circuit on said silicon substrate;
a dielectric layer over said silicon substrate;
a fine-line metallization structure over said silicon substrate and in said dielectric layer, wherein said fine-line metallization structure comprises a first interconnecting structure connected to said ESD circuit, and a second interconnecting structure connected to said internal circuit, and wherein said fine-line metallization structure comprises a copper line and a first adhesion layer at a bottom of said copper line and at a sidewall of said copper line;
a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride layer;
a first via in said passivation layer, wherein said first via is connected to said first interconnecting structure;
a second via in said passivation layer, wherein said second via is connected to said second interconnecting structure; and
a third interconnecting structure over said passivation layer, wherein said third interconnecting structure is connected to said first and second vias, wherein said ESD circuit is connected to said internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure, wherein said third interconnecting structure comprises a second adhesion layer, a seed layer on said second adhesion layer, and an electroplated metal layer on said seed layer, wherein said electroplated metal layer has a sidewall not covered by said second adhesion layer.
10. The chip of claim 9 , wherein said nitride layer has a thickness greater than 0.3 micrometers.
11. The chip of claim 9 , wherein said nitride layer comprises an oxynitride.
12. The chip of claim 9 , wherein said third interconnecting structure comprises a power bus over said passivation layer, wherein said ESD circuit is connected to said internal circuit through said power bus.
13. The chip of claim 9 , wherein said third interconnecting structure comprises a ground bus over said passivation layer, wherein said ESD circuit is connected to said internal circuit through said ground bus.
14. The chip of claim 9 , wherein said electroplated metal layer comprises copper.
15. The chip of claim 9 , wherein said second adhesion layer comprises titanium.
16. A chip comprising:
a silicon substrate;
a first internal circuit on said silicon substrate;
a second internal circuit on said silicon substrate;
a dielectric layer over said silicon substrate;
a fine-line metallization structure over said silicon substrate and in said dielectric layer, wherein said fine-line metallization structure comprises a first interconnecting structure connected to said first internal circuit, and a second interconnecting structure connected to said second internal circuit, wherein said fine-line metallization structure comprises a copper line and a first adhesion layer at a bottom of said copper line and at a sidewall of said copper line;
a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride layer;
a first via in said passivation layer, wherein said first via is connected to said first interconnecting structure;
a second via in said passivation layer, wherein said second via is connected to said second interconnecting structure; and
a third interconnecting structure over said passivation layer, wherein said third interconnecting structure is connected to said first and second vias, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure, wherein said third interconnecting structure comprises a second adhesion layer, a seed layer on said second adhesion layer, and an electroplated metal layer on said seed layer, wherein said electroplated metal layer has a sidewall not covered by said second adhesion layer.
17. The chip of claim 16 , wherein said nitride layer has a thickness greater than 0.3 micrometers.
18. The chip of claim 16 , wherein said nitride layer comprises an oxynitride.
19. The chip of claim 16 further comprising a polymer layer over said passivation layer, wherein said polymer layer has a portion over said third interconnecting structure.
20. The chip of claim 16 , wherein said electroplated metal layer comprises copper.