Programmable element and manufacturing method of semiconductor device
View Patent ↗In one aspect of the present invention, a programmable element, may include a semiconductor substrate, source/drain layers formed apart from each other in the upper surface of the semiconductor substrate, a gate insulating film including a charge-trapping film containing Hf and formed on a portion between the source/drain layers of the semiconductor substrate, and a gate electrode formed on the gate insulating film with a program voltage applied to the gate electrode.
1. A programmable element, comprising:
a semiconductor substrate;
source/drain layers formed apart from each other in an upper surface of the semiconductor substrate;
a gate insulating film including a charge-trapping film containing Hf and formed on a portion between the source/drain layers of the semiconductor substrate; and
a gate electrode formed on the gate insulating film with a program voltage applied to the gate electrode,
wherein the charge-trapping film contains Si, and an atomic concentration of Hf contained in the charge-trapping film is 30 percent or more of a total atomic concentration of Hf and Si contained in the charge-trapping film.
2. The programmable element according to claim 1 , wherein the interlayer is SiO 2 .
3. The programmable element according to claim 1 , wherein a thickness of the charge-trapping film is 4 nm or more.
4. The programmable element according to claim 1 , wherein a voltage of 3 V or less is applied to the gate electrode as the program voltage and thereby the programmable element is controlled.
5. The programmable element according to claim 1 , wherein the charge-trapping film is HfSiON and an upper gate insulating film is provided on the charge-trapping film.
6. The programmable element according to claim 5 , wherein the upper gate insulating film is HfSiO.
7. The programmable element according to claim 6 , wherein an atomic concentration in the charge-trapping film the upper gate insulating layer is 30 percent or more of a total atomic concentration of Hf and Si contained in the charge-trapping film and the upper gate insulating layer.
8. A programmable element, comprising:
a semiconductor substrate;
source/drain layers formed apart from each other in an upper surface of the semiconductor substrate;
a gate insulating film including a charge-trapping film containing Hf and formed on a portion between the source/drain layers of the semiconductor substrate;
a gate electrode formed on the gate insulating film with a program voltage applied to the gate electrode; and
an interlayer interposed between the semiconductor substrate and the gate insulating film, wherein a thickness of the interlayer is 1 nm or less.
9. The programmable element according to claim 8 , wherein the charge-trapping film contains Si, and an atomic concentration of Hf contained in the charge-trapping film is 30 percent or more of a total atomic concentration of Hf and Si contained in the charge-trapping film.
10. The programmable element according to claim 8 , wherein a thickness of the charge-trapping film is 4 nm or more.
11. The programmable element according to claim 8 , wherein a voltage of 3 V or less is applied to the gate electrode as the program voltage and thereby the programmable element is controlled.
12. The programmable element according to claim 8 , wherein the charge-trapping film is HfSiON and an upper gate insulating film is provided on the charge-trapping film.
13. The programmable element according to claim 8 , wherein an atomic concentration in the charge-trapping film the upper gate insulating layer is 30 percent or more of a total atomic concentration of Hf and Si contained in the charge-trapping film and the upper gate insulating layer.
14. A programmable element, comprising:
a semiconductor substrate;
source/drain layers formed apart from each other in an upper surface of the semiconductor substrate;
a gate insulating film including a charge-trapping film containing Hf and formed on a portion between the source/drain layers of the semiconductor substrate; and
a gate electrode formed on the gate insulating film with a program voltage applied to the gate electrode,
wherein the charge-trapping film is HfSiON and an upper gate insulating layer is HfSiO and provided on the charge-trapping film, and an atomic concentration in the charge-trapping film, the upper gate insulating layer is 30 percent or more of a total atomic concentration of Hf and Si contained in the charge-trapping film and the upper gate insulating layer.
15. The programmable element according to claim 14 , wherein a thickness of the charge-trapping film is 4 nm or more.
16. The programmable element according to claim 14 , wherein a voltage of 3 V or less is applied to the gate electrode as the program voltage and thereby the programmable element is controlled.