Temperature sensor circuit and calibration method thereof

1. A semiconductor device comprising:

a temperature sensor circuit that includes:

a first monitor voltage generation circuit that generates a first monitor voltage with a characteristic that changes with respect to temperature;

a second monitor voltage generation circuit that generates a second monitor voltage with a characteristic that changes by a variation amount different from the first monitor voltage with respect to the temperature; and

a differential amplifier circuit, to which the first and second monitor voltages are inputted and that outputs a result of comparing the two voltages,

wherein the differential amplifier circuit is capable of switching to a first connection state to output the comparison result for controlling a refresh cycle of a memory, and to a second connection state to output an offset monitor voltage by adding an offset voltage of the differential amplifier circuit to one of the first and second monitor voltages or subtracting the offset voltage therefrom.

2. The semiconductor device according to claim 1 , further comprising: an output buffer circuit to which the offset monitor voltage or the first or second monitor voltage is inputted and that amplifies the voltage thus inputted to output.

3. The semiconductor device according to claim 1 , wherein the memory includes a DRAM memory cell, array.

4. The semiconductor device according to claim 1 , wherein the second connection state is a state where an input of the other of the first and second monitor voltages to one input terminal of the differential amplifier circuit is prohibited and where a negative feedback circuit is provided to the one input terminal from the output of the differential amplifier circuit.

5. The semiconductor device according to claim 4 , wherein the negative feedback circuit comprises: an output transistor to a gate of which the output of the differential amplifier circuit is connected; and feedback wiring that connects a drain of the output transistor to the one input terminal of the differential amplifier circuit.

6. The semiconductor device according to claim 1 , wherein the second connection state includes: a state where a first offset monitor voltage, which is rendered by adding the offset voltage to one of the first and second monitor voltage, is outputted; a state where a second offset monitor voltage, which is rendered by subtracting the offset voltage from one of the first and second monitor voltage, is outputted; and a state where a third offset monitor voltage, which is rendered by adding the offset voltage to the other of the first and second monitor voltages or subtracting the offset voltage therefrom, is outputted.

7. The semiconductor device according to claim 6 , wherein the second connection state is a state where the input of the other of the first and second monitor voltages to one input terminal of the differential amplifier circuit is prohibited and where a negative feedback circuit that comprises an output transistor and feedback wiring is provided to connect the output of the differential amplifier circuit to the one input terminal.

8. The semiconductor device according to claim 7 , further comprising: first and second switches that connect each of the first and second monitor voltages to the noninverting input terminal or inverting input terminal of the differential amplifier circuit; a fifth switch that connects the output terminal of the differential amplifier circuit to the comparison result output terminal or output transistor; and a sixth switch that connects the drain of the output transistor to the noninverting input terminal or inverting input terminal of the differential amplifier circuit.

9. A calibration method for a temperature sensor circuit provided in a semiconductor device comprising:

generating a first monitor voltage with a characteristic that changes with respect to temperature;

generating a second monitor voltage with a characteristic that changes by a variation amount different from the first monitor voltage with respect to the temperature;

comparing the first and second monitor voltages to output a result of comparing the two voltages; and

switching between a first connection state to output the comparison result to control a refresh cycle of a memory and a second connection state to output an offset monitor voltage by adding an offset voltage of the differential amplifier circuit to one of the first and second monitor voltage or subtracting the offset voltage therefrom.

10. The calibration method according to claim 9 , wherein the memory includes a DRAM memory cell array.

11. The calibration method according to claim 9 , further comprising:

detecting a first-temperature state offset monitor voltage by establishing the second connection state and adding the offset voltage to the first or second monitor voltage or subtracting the offset voltage therefrom in a first temperature state;

detecting a second-temperature state offset monitor voltage adding the offset voltage to the first or second monitor voltage or subtracting the offset voltage therefrom in a second temperature state that differs from the first temperature state; and

trimming circuit elements to generate the first or second monitor voltage so that a detection temperature determined on the basis of the first, and second-temperature state offset monitor voltages becomes a desired detection temperature.

12. The calibration method according to claim 11 , further comprising:

detecting, in the first and second temperature states respectively, the temperature state offset monitor voltage for one of the first and second monitor voltages in correspondence with a plurality of trimming values with respect to circuit elements.