Method of fabricating non-volatile memory device with concavely depressed electron injection region

1. A method of fabricating a non-volatile memory device, the method comprising:

forming an oxide layer and a nitride layer on a semiconductor substrate;

forming a first nitride layer pattern by selectively etching the nitride layer;

doping the semiconductor substrate with first impurities using the first nitride layer pattern as a mask to form an electron injection region;

forming a partial oxide layer pattern thicker than the oxide layer by oxidizing the electron injection region;

forming a second nitride layer pattern by selectively etching the first nitride layer pattern;

etching the semiconductor substrate using the second nitride layer pattern and the partial oxide layer pattern as a mask to form a trench around the electron injection region;

forming a device isolation layer pattern by gap-filling the trench with a dielectric and then removing the second nitride layer pattern;

forming a control gate region by selectively implanting the semiconductor substrate with second impurities;

selectively etching the partial oxide layer pattern and a portion of the device isolation layer pattern to expose a top surface and a side surface of the electron injection region;

forming a first tunnel oxide layer and a second tunnel oxide layer by re-oxidizing an entire surface of the semiconductor substrate, the first tunnel oxide layer being on the control gate region, the second tunnel oxide layer being on the top surface and the side surface of the electron injection region; and

forming a floating gate electrode covering at least a portion of the control gate region and an edge of the electron injection region,

wherein the top surface of the electron injection region has an area concavely depressed, and

wherein a portion of the floating gate is disposed in the concavely depressed area of the electron injection region.

2. The method according to claim 1 , further comprising, before the forming of the control gate region:

forming a second impurity well region below the electron injection region by selectively implanting the semiconductor substrate with second impurities; and

forming a first impurity well region by selectively implanting the semiconductor substrate with first impurities.

3. The method according to claim 2 , wherein the control gate region is formed on a portion of the first impurity well region.

4. The method according to claim 1 , wherein the edge of the electron injection region comprises a tip portion formed during the exposing of the top surface and side surface of the electron injection region.

5. The method according to claim 4 , wherein the device isolation layer pattern comprises a groove having a depth lower than the tip portion.

6. The method according to claim 1 , further comprising:

during the forming of the trench around the electron injection region, etching the semiconductor substrate using the second nitride layer pattern as a mask to form a second trench defining an active area between the trench around the electron injection region and the control gate region;

forming a second isolation layer pattern by gap filling the second trench with the dielectric; and

after forming the floating gate electrode, forming a source and drain region for the floating gate electrode in the active area.