Method of manufacturing flash memory device with reduced void generation
View Patent ↗A method of manufacturing a flash memory device that may include forming a first oxide film pattern and a first polysilicon pattern on a semiconductor substrate; sequentially forming a dielectric film pattern and a second polysilicon pattern on the semiconductor substrate including the first oxide film pattern and the first polysilicon pattern; forming a second oxide film pattern on the second polysilicon pattern; forming a gate by etching to the semiconductor substrate using the second oxide film pattern as a mask, the gate including the first oxide film pattern, the first polysilicon pattern, the dielectric film pattern and the second polysilicon pattern; removing the second oxide film pattern; forming a spacer on sidewalls of the gate; and forming an interlayer dielectric film on the semiconductor substrate including the gate and the spacer.
1. A method comprising:
forming a first oxide film pattern and a first polysilicon pattern on a semiconductor substrate;
sequentially forming a dielectric film and a polysilicon film on the semiconductor substrate including the first oxide film pattern and the first polysilicon pattern;
forming a second oxide film pattern on the polysilicon film;
forming a gate by etching to the semiconductor substrate using the second oxide film pattern as a mask, the gate including the first oxide film pattern, the first polysilicon pattern, a dielectric film pattern and a second polysilicon pattern;
removing the second oxide film pattern;
forming a spacer on sidewalls of the gate; and
forming an interlayer dielectric film on the semiconductor substrate including the gate and the spacer,
wherein forming the spacer comprises:
forming a third oxide film and a first nitride film on the sidewalls of the gate;
forming a third oxide film pattern and a first nitride pattern on the sidewalls of the gate by performing a dry-etching process on the third oxide film and the first nitride film;
removing the first nitride film pattern;
forming a second nitride film on the semiconductor substrate including the third oxide film pattern and the gate;
forming a fourth oxide film on the second nitride film; and
forming a second nitride film pattern by performing an etching process on the fourth oxide film.
2. The method of claim 1 , wherein the second oxide film pattern is made of TEOS.
3. The method of claim 1 , wherein the second oxide film pattern is removed using hydrogen fluoride (HF) solution.
4. The method of claim 1 , wherein the second oxide film pattern is removed through a vapor phase cleaning process.
5. The method of claim 4 , wherein the vapor phase cleaning process is performed at a temperature of 39° C.
6. The method of claim 4 , wherein the vapor phase cleaning process is performed for 10 to 20 seconds.
7. The method of claim 1 , wherein the second oxide film pattern is formed at a thickness in a range between 2000 to 2200 Å.
8. The method of claim 1 , wherein the spacer comprises the third oxide film pattern and the second nitride film pattern.
9. The method of claim 1 , wherein the third oxide film is formed at a thickness in a range between 150 to 250 Å.
10. The method of claim 1 , wherein the first nitride film is formed at a thickness in a range between 770 to 1500 Å.
11. The method of claim 1 , wherein the second nitride film is formed at a thickness in a range between 180 to 220 Å.
12. The method of claim 1 , further comprising, before forming the interlayer dielectric film and after forming the spacer:
depositing a silicide-forming metal over the overall surface of the semiconductor substrate including the gate and the spacer; and then
forming a metal silicide layer on the gate by performing an annealing process on the semiconductor substrate including the silicide-forming metal.
13. The method of claim 12 , wherein the silicide-forming metal comprises cobalt.