IP Library Patent Application 12147370
Patent Application
App. No. 12/147,370

SEMICONDUCTOR WITH TOP-SIDE WRAP-AROUND FLANGE CONTACT

Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US None
App. No.
12/147,370
Abstract

A method and apparatus are described for an electronic component package. A standoff is formed on an active side of a substrate. The substrate has an electronic circuit. A conductive layer is deposited over at least a portion of the active side of the substrate. The conductive layer electrically couples a contact area on the active side of the substrate. The standoff is removed to create a flexible conductor.

Claims (46)

1 . A method of making an electronic component package, the method comprising:

forming a standoff on an active side of a substrate, the substrate having an electronic circuit;

depositing a conductive layer over at least a portion of the standoff and a portion of the active side of the substrate, the conductive layer electrically coupling a contact area on the active side of the substrate; and

removing the standoff to create a flexible conductor.

2 . The method of claim 1 , further comprising:

depositing an insulating layer on the active side of the substrate prior to forming the standoff, wherein the contact area remains exposed.

3 . The method of claim 1 , wherein the standoff is formed by depositing standoff material through a stencil.

4 . The method of claim 1 , wherein forming the standoff comprises:

depositing an encapsulant on the active side of the substrate; and

photoforming or etching a portion of the encapsulant to expose the contact area.

5 . The method of claim 1 , wherein forming the standoff comprises:

attaching a prefabricated standoff.

6 . The method of claim 1 , wherein the standoff comprises a polymer.

7 . The method of claim 1 , wherein the standoff is between 25 and 200 microns in height.

8 . The method of claim 1 , wherein the conductive layer comprises one or more of the following: gold, silver, nickel, titanium, tungsten, aluminum, copper, platinum.

9 . The method of claim 1 , wherein the conductive layer comprises a top layer to accept solder and a bottom layer to reject solder.

10 . The method of claim 1 , further comprising:

encapsulating the electronic component package and a second component within a single assembly;

electrically coupling the conductive layer of the electronic component package with a contact on the second component by plating the encapsulated assembly using build-up processing.

11 . The method of claim 1 , wherein a barrier metal layer is deposited, prior to the conductive layer, on at least a portion of the area to be covered by the conductive layer.

12 . The method of claim 1 , wherein the standoff is removed by an etching process.

13 . The method of claim 1 , further comprising:

depositing a second insulation layer on the active side of the substrate after removing the standoff, wherein a portion of the flexible conductor remains exposed.

14 . The method of claim 13 , wherein the second insulation layer is deposited using a masking process.

15 . The method of claim 13 , wherein the second insulation layer is deposited uniformly over the entire electronic component package and removed from an upper portion of the flexible conductor.

16 . The method of claim 1 , further comprising:

depositing an encapsulant on a non-active side of the substrate.

17 . The method of claim 1 , further comprising:

coupling the flexible conductor with a printed circuit board using one or more of the following: solder, ultrasonic bonding, conductive epoxy, or plated conductors.

18 . An electronic component package comprising:

a flexible flange contact on an active side of a substrate, the substrate having an electronic circuit, wherein a gap of air defines the space between a portion of the contact and a portion of the active side of the substrate.

19 . The electronic component package of claim 18 , further comprising:

an insulating layer on the active side of the substrate between the active side of the substrate and the gap of air and between the active side of the substrate and a portion of the contact, wherein the contact is electrically coupled with the active side of the substrate through the insulating layer.

20 . The electronic component package of claim 18 , wherein the gap of air between the portion of the contact and the portion of the active side of the substrate is between 25 and 200 microns in height.

21 . The electronic component package of claim 18 , wherein the contact comprises one or more of the following: gold, silver, nickel, titanium, tungsten, aluminum, copper, platinum.

22 . The electronic component package of claim 18 , wherein

the electronic component package and a second component is encapsulated within a single assembly, and

the conductive layer of the electronic component package is electrically coupled with a contact on the second component by plating the encapsulated assembly using build-up processing.

23 . The electronic component package of claim 18 , wherein the contact comprises a top layer to accept solder and a bottom layer to reject solder.

24 . The electronic component package of claim 18 , further comprising:

a barrier metal layer on the substrate side of the contact.

25 . The electronic component package of claim 18 , further comprising:

a second insulation layer on the active side of the substrate covering a portion of the contact, wherein the gap of air defines the space between a portion of the contact and a portion of the second insulation layer.

26 . The electronic component package of claim 25 , wherein the gap of air between a portion of the contact and a portion of the second insulation layer is between 10 and 100 microns in height.

27 . The electronic component package of claim 18 , further comprising:

an encapsulant on a non-active side of the substrate.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 22, 2009
From: CHIPSCALE, INC.
To: WAFER-LEVEL PACKAGING PORTFOLIO LLC
Reel/Frame 022142/0718 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 25, 2008
From: MARCOUX, PHIL P., MR.
To: CHIPSCALE, INC.
Reel/Frame 021588/0088 →