Debugging system and method including an emulator for debugging a target device
View Patent ↗A debugging system includes an emulator connected via a communication line for two-way communication and a target device to be debugged by the emulator. The emulator includes a serial signal transmitting unit to transmit a control signal as serial data to the target device and an A/D converter to convert an analog signal into a digital signal and to output the digital signal, the analog signal is input from the target device via the communication line. The target device includes a trace circuit, a serial signal receiving unit to receive the serial data and a D/A converter to convert, in response to the control signal received, trace information into an analog signal, and to output the analog signal, the trace information is output by the trace circuit.
1. A debugging system, comprising:
an emulator connected via a communication line for two-way communication; and
a target device to be debugged by the emulator,
wherein the emulator includes:
a serial signal transmitting unit to transmit a control signal to the target device; and
an A/D converter to convert an analog signal into a digital signal and to output the digital signal, the analog signal being input from the target device via the communication line, and
wherein the target device includes:
a trace circuit;
a serial signal receiving unit to receive the control signal; and
a D/A converter to convert, in response to the control signal received, trace information into an analog signal, and to output the analog signal, the trace information being output by the trace circuit.
2. The debugging system according to claim 1 , wherein the emulator further includes a memory unit to store a maximum voltage output by the target device and a maximum value of digital data output by the serial signal transmitting unit so as to be associated with each other.
3. The debugging system according to claim 1 , wherein the D/A converter divides the trace information converted into the analog signal, and outputs the analog signal.
4. The debugging system according to claim 1 , wherein the emulator forcibly terminates reception of the trace information converted into the analog signal.
5. A debugging circuit, comprising:
the trace circuit according to claim 1 serving as a CPU.
6. The debugging system according to claim 1 , wherein the control signal is output from a host machine placed in the emulator through a host interface to control the target device.
7. The debugging system according to claim 1 , further comprising:
an emulator OCD (on-chip debug) circuit for outputting the control signal to the serial signal transmitting unit.
8. The debugging system according to claim 7 , wherein the A/D converter converts the trace information output by the target device as the analog signal into the digital signal to be output to the emulator OCD circuit.
9. The debugging system according to claim 7 , wherein the serial signal transmitting unit transmits the control signal received from the emulator OCD circuit to the serial signal receiving unit.
10. The debugging system according to claim 7 , wherein the emulator OCD circuit transmits a break command to the trace circuit at predetermined intervals such that the emulator executes a forced break operation for the trace circuit when a malfunction occurs.
11. The debugging system according to claim 7 , wherein the emulator further comprises:
a trace memory to store the trace information as the digital data,
wherein after the A/D converter converts the trace information into the digital data, the trace information is output to the emulator OCD circuit and then the emulator OCD circuit outputs the trace information to the trace memory.
12. The debugging system according to claim 1 , wherein the serial signal transmitting unit transmits the control signal to the serial signal receiving unit as the digital signal.
13. The debugging system according to claim 1 , further comprising:
a target device OCD (on-chip debug) circuit that receives the control signal from the serial signal receiving unit.
14. The debugging system according to claim 13 , wherein the target device OCD circuit controls the trace circuit in response to the control signal received by the target device OCD circuit.
15. The debugging system according to claim 13 , wherein the trace circuit outputs the trace information in response to an output of the control signal from the target device OCD circuit.
16. The debugging system according to claim 13 , wherein the D/A converter converts the trace information input from the target device OCD circuit as the digital data into the analog signal.
17. A debugging method of debugging a program stored in a target device externally via a communication line, said method comprising:
inputting a control signal to the target device via the communication line;
converting a digital signal associated with trace data of the target device into an analog signal; and
receiving the analog signal via the communication line.
18. The debugging method according to claim 17 , further comprising:
associating a maximum value of a voltage output by the target device with a maximum value of the digital signal to convert the analog signal received into digital data.
19. The debugging method according to claim 18 , wherein the converting of the digital signal associated with the trace data into the analog signal is performed in the target device.
20. The debugging method according to claim 17 , wherein the converting of the digital signal associated with the trace data into the analog signal is performed in the target device.