IP Library Granted Patent US 7,859,808
Granted Patent B2
US 7,859,808 · App. 12/149,577 · Granted Dec 28, 2010

Electrostatic protection circuit

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Quick Facts
Patent No.
US 7,859,808
App. No.
12/149,577
Granted
Dec 28, 2010
Kind
B2
Abstract

An electrostatic protection circuit, includes a first terminal, a second terminal, a MOS transistor including a gate, a source, and a drain, the gate being coupled to the first terminal, the source being coupled to the second terminal, and an electrostatic protection element connected to the drain, wherein the electrostatic protection element includes a first electrostatic protection element, and a second electrostatic protection element connected between the first terminal and the second terminal. The electrostatic protection circuit is constructed such that a maximum value of a voltage applied to a gate insulating film of the MOS transistor is alleviated to a value equal to or smaller than a desirable value by a current flowing into the first electrostatic protection element at a time of electrostatic application to the first terminal and an internal parasitic resistance of the MOS transistor connected with the second terminal.

Claims (21)

1. An electrostatic protection circuit, comprising:

a first terminal;

a second terminal;

a MOS transistor including a gate, a source, and a drain, the gate being coupled to the first terminal, the source being coupled to the second terminal;

an electrostatic protection element connected to the drain, wherein the electrostatic protection element comprises a first electrostatic protection element; and

a second electrostatic protection element connected between the first terminal and the second terminal,

wherein the electrostatic protection circuit is constructed such that a maximum value of a voltage applied to a gate insulating film of the MOS transistor is alleviated to a value equal to or smaller than a desirable value by a current flowing into the first electrostatic protection element at a time of electrostatic application to the first terminal and an internal parasitic resistance of the MOS transistor connected with the second terminal.

2. The electrostatic protection circuit according to claim 1 wherein:

the first terminal comprises one of an input terminal and a power supply terminal;

the second terminal comprises one of a power supply terminal and a ground terminal;

the electrostatic protection circuit further comprises an input circuit receiving an input at the input terminal; and

the MOS transistor is included in the input circuit.

3. The electrostatic protection circuit according to claim 2 , wherein:

the input circuit comprises a differential amplifier for input which includes transistors as a differential pair; and

the MOS transistor comprises one of the transistors of the differential amplifier.

4. The electrostatic protection circuit according to claim 2 , wherein:

the input circuit comprises a differential amplifier for input which includes transistors as a differential pair; and

the MOS transistor comprises one of the transistors of the differential amplifier which is connected as a current source with the input terminal.

5. The electrostatic protection circuit according to claim 1 , further comprising a circuit provided between the first protection element and the first terminal,

wherein a current flowing into the circuit flows into the first electrostatic protection circuit.

6. A semiconductor device, comprising the electrostatic protection circuit according to claim 1 .

Assignments (3)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
CHANGE OF NAME Recorded Oct 28, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025214/0696 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 5, 2008
From: OKUSHIMA, MOTOTSUGU
To: NEC ELECTRONICS CORPORATION
Reel/Frame 020953/0044 →