Magnetic random access memory with selective toggle memory cells
View Patent ↗A toggle MTJ is disclosed that has a SAF free layer with two or more magnetic sub-layers having equal magnetic moments but different anisotropies which is achieved by selecting Ni ˜0.8 Fe ˜0.2 for one sub-layer and CoFeB or the like with a uni-axial anisotropy of 10 to 30 Oe for the higher anisotropy sub-layer. When a field is applied at <10° angle from the easy axis, magnetic vectors for the two sub-layers rotate to form different angles from the easy axis. A method is also described for selectively writing to bits along a word line that is orthogonal to bit line segments and avoids the need to “read first”. A bipolar word line pulse with two opposite pulses separated by a no pulse interval is applied in the absence of a bit line pulse to write a “0”. A bit line pulse opposite the second word line pulse writes a “1”.
1. A method of selectively writing to a toggle MTJ cell formed between a bit line and word line in a crossover region in a MRAM array wherein the word line and bit line are aligned at the same 45° to 60° angle relative to an easy axis of a SAF free layer in said toggle MTJ cell, said SAF free layer has a plurality of “n” magnetic sub-layers including an inner sub-layer and an outer sub-layer with equal magnetic moments wherein “n” is an even integer and the inner sub-layer or the outer sub-layer has a greater anisotropy than the other sub-layers, and an anti-parallel coupling layer between adjacent magnetic sub-layers, comprising:
(a) applying a word line current pulse and a matching bit line current pulse during a first time interval wherein the sum of the magnetic fields generated by said pulses is parallel to the easy axis and is larger than the spin-flop field of the SAF free layer with sufficient margin to write a memory state; and
(b) reducing the word line current pulse and the bit line current pulse in a matching manner to zero with a falling edge design during a second time interval.
2. The method of claim 1 wherein the sum of the fields generated by the word line current pulse and bit line current pulse is in a first direction along the easy axis and writes a “1” memory state.
3. The method of claim 2 wherein the sum of the fields generated by the word line current pulse and bit line current pulse is in a second direction opposite the first direction and writes a “0” memory state.
4. The method of claim 1 wherein said falling edge design has a “longer current falling time” configuration.
5. The method of claim 1 wherein said falling edge design has a “multi-step falling edge” configuration.
6. The method of claim 1 wherein the sum of the magnetic fields is applied in a direction that is less than an angle of about 10 degrees away from the easy axis.