Three-dimensional phase-change memory array
View Patent ↗A three-dimensional phase-change memory array. In one embodiment of the invention, the memory array includes a first plurality of diodes, a second plurality of diodes disposed above the first plurality of diodes, a first plurality phase-change memory elements disposed above the first and second plurality of diodes and a second plurality of memory elements disposed above the first plurality of memory elements.
1. A memory array comprising:
a substrate;
a first phase-change memory cell disposed over said substrate, said first phase-change memory cell including a first lower contact in series with a first phase-change layer and a first upper contact in series with said first phase-change layer, said first phase-change layer being interposed between said first lower contact and said first upper contact; and
a second phase-change memory cell disposed over said substrate, said second phase-change memory cell including a second lower contact in series with a second phase-change layer and a second upper contact in series with said second phase-change layer, said second phase-change layer being interposed between said second lower contact and said second upper contact;
wherein said second lower contact is disposed between said first lower contact and said first upper contact.
2. The memory array of claim 1 , wherein said second lower contact is disposed above said first phase-change layer.
3. The memory array of claim 1 , wherein said first phase-change layer is disposed above said first lower contact and said second phase-change layer is disposed above said second lower contact.
4. The memory array of claim 1 , wherein said first phase-change memory cell further includes a first isolation device in series with said first phase-change layer, said first isolation device being interposed between said first lower contact and said first upper contact and wherein said second phase-change memory cell further includes a second isolation device in series with said second phase-change layer, said second isolation device being interposed between said second lower contact and said second upper contact.
5. The memory array of claim 4 , wherein said first isolation device is a diode or transistor.
6. The memory array of claim 4 , wherein said first isolation device is a threshold switch.
7. The memory array of claim 4 , wherein a first conductive plug interconnects said first isolation device and said first phase-change layer.
8. The memory array of claim 7 , wherein a second conductive plug interconnects said second isolation device and said second phase-change layer.
9. The memory array of claim 8 , wherein said first conductive plug is electrically isolated from said second conductive plug.
10. The memory array of claim 4 , wherein the projection of said second isolation device onto said substrate overlaps the projection of said first isolation device onto said substrate.
11. The memory array of claim 1 , wherein said second lower contact is electrically isolated from said first upper contact.
12. The memory array of claim 1 , wherein a dielectric material is disposed between said second lower contact and said first upper contact.
13. The memory array of claim 1 , wherein said second lower contact is disposed between said first lower contact and said first phase-change layer.
14. The memory array of claim 1 , wherein said second upper contact is disposed above said first upper contact.
15. The memory array of claim 1 , wherein the projection of said second phase-change layer onto said substrate overlaps the projection of said first phase-change layer onto said substrate.