Granted Patent B2

US 8,370,113 · App. 12/152,843 · Granted Feb 5, 2013

Abstract

Claims (73)

1. A system comprising:

an averaging persistence filter configured to capture a persistent portion of a digital signal and to remove a non-persistent portion of the digital signal, the averaging persistence filter comprising:

an interface configured to receive the digital signal; and

one or more processors, coupled to the interface, configured to:

aggregate a plurality of digital signal sample sets of the digital signal to generate aggregated results;

scale the aggregated results using selective ones of a plurality of coefficients to generate a plurality of linear reference components of the digital signal;

aggregate the plurality of linear reference components; and

determine an output based on the aggregated plurality of linear reference components.

2. The system of claim 1 , wherein the one or more processors include a shared multiplier that is shared by at least some of the plurality of coefficients.

3. The system of claim 1 , wherein the one or more processors are further configured to determine a sum of R digital signal samples during a time cycle.

4. The system of claim 3 , wherein the sum is multiplied with a selected one of the plurality of coefficients.

5. The system of claim 1 , wherein the one or more processors include a shared multiplier, and wherein the one or more processors are further configured to:

determine a first sum of R digital signal samples during a first time cycle;

multiply the first sum with a selected first one of the plurality of coefficients using the shared multiplier to obtain a first product;

determine a second sum of R digital signal samples during a second time cycle; and

multiply the second sum with a selected second one of the plurality of coefficients using the shared multiplier to obtain a second product.

6. The system of claim 5 , wherein the one or more processor further comprise: an accumulator, and wherein the one or more processors are further configured to aggregate the first product and the second product using the accumulator.

7. The system of claim 1 , wherein the digital signal has an input data rate, and wherein the output has an output data rate that is 1/R of the input data rate, R being an integer that is greater than one.

8. The system of claim 7 , wherein the system has a speed of convergence that is proportional to the input data rate.

9. A signal processing method, comprising:

inputting a digital signal at an interface of an averaging persistence filter;

aggregating a plurality of digital signal sample sets of the digital signal to generate aggregated results;

scaling the aggregated results using selective ones of a plurality of coefficients to generate a plurality of linear reference components of the digital signal;

aggregating the plurality of linear reference components; and

determining an output based on the aggregated plurality of linear reference components,

a persistent portion of the digital signal being included in the output and a non-persistent portion of the digital signal being removed from the output.

10. The method of claim 9 , wherein the determining the output comprises: determining a sum of R digital signal samples during a time cycle.

11. The method of claim 10 , wherein the determining the output further comprises: multiplying the sum with a selected one of the plurality of coefficients.

12. The method of claim 9 , wherein the determining the output comprises:

determining a first sum of R digital signal samples during a first time cycle;

multiplying the first sum with a first selected one of the plurality of coefficients using a shared multiplier to obtain a first product;

determining a second sum of R digital signal samples during a second time cycle; and

multiplying the second sum with a second selected one of the plurality of coefficients using the shared multiplier to obtain a second product.

13. The method of claim 12 , wherein the determining the output further comprises: aggregating the first product and the second product using an accumulator.

14. The method of claim 9 , wherein the inputting the digital signal comprises: inputting the digital signal having an input data rate, and wherein the determining the output comprises: determining the output having an output data rate that is 1/R of the input data rate, R being an integer that is greater than one.

15. A non-transitory computer-readable storage medium having instructions stored thereon, execution of which, by a computing device, causes the computing device to perform operations comprising:

aggregating a plurality of digital signal sample sets of a digital signal to generate aggregated results;

scaling the aggregated results using selective ones of a plurality of coefficients to generate a plurality of linear reference components of the digital signal;

aggregating the plurality of linear reference components; and

determining an output based on the aggregated plurality of linear reference components,

a persistent portion of the digital signal being included in the output and a nonpersistent portion of the digital signal being removed from the output.

16. A signal processing system comprising:

an input interface configured to receive a digital signal having a distorted component and an undistorted component; and

a separation block coupled to the input interface, configured to separate from the digital signal a reference component and a target component,

the separation block including a filter configured to:

aggregate a plurality of digital signal sample sets of the digital signal;

scale aggregated results using selective ones of a plurality of coefficients to generate a plurality of linear reference components of the digital signal;

aggregate the plurality of linear reference components; and

determine a filter output based on the aggregated plurality of linear reference components;

wherein the filter is further configured to capture a persistent portion of the digital signal and to remove a non-persistent portion of the digital signal.

17. The signal processing system of claim 16 , wherein the separation block is further configured to determine an error signal that corresponds to a difference between the filter output and a sum of a plurality of consecutive samples of the digital signal.

18. The signal processing system of claim 17 , wherein the error signal is fed back to the filter to adapt the plurality of coefficients.

19. The signal processing system of claim 16 , wherein the filter comprises: a shared multiplier that is shared by at least some of the plurality of coefficients.

20. The signal processing system of claim 16 , wherein the filter is configured to determine a sum of R digital signal samples during a time cycle.

21. The signal processing system of claim 16 , further comprising: an adaptive filter, coupled to the separation block, configured to adaptively generate, based on the reference component, a replica distortion signal that is substantially similar to the distorted component.

22. A method of signal processing, comprising:

receiving, at an interface of an averaging persistence filter, a digital signal having a distorted component and an undistorted component; and

separating from the digital signal a reference component that corresponds to a persistent portion of the digital signal and a target component that corresponds to a difference of the digital signal and the reference signal, the separating including:

aggregating a plurality of digital signal sample sets of the digital signal to generate aggregated results;

scaling the aggregated results using selective ones of a plurality of coefficients to generate a plurality of linearly enhanced components of the digital signal;

aggregating the plurality of linearly enhanced components; and

generating the reference component based on the aggregated plurality of linearly enhanced components.

23. The method of claim 22 , further comprising: determining an error signal that corresponds to a difference between the filter output and a sum of a plurality of consecutive samples of the digital signal.

24. The method of claim 23 , further comprising: feeding back the error signal; and adapting the plurality of coefficients.

25. The method of claim 22 , further comprising: determining a sum of R digital signal samples during a time cycle.

26. The method of claim 22 , further comprising: adaptively generating, based on the reference component, a replica distortion signal that is substantially similar to the distorted component.

27. A non-transitory computer-readable storage medium having instructions stored thereon, execution of which, by a computing device, causes the computing device to perform operations comprising:

receiving a digital signal having a distorted component and an undistorted component; and

separating from the digital signal a reference component that corresponds to a persistent portion of the digital signal and a target component that corresponds to a difference of the digital signal and the reference signal, the separating including:

aggregating a plurality of digital signal sample sets of the digital signal to generate aggregated results;

scaling the aggregated results using selective ones of a plurality of coefficients to generate a plurality of linearly enhanced components of the digital signal;

aggregating the plurality of linearly enhanced components; and

generating the reference component based on the aggregated plurality of linearly enhanced components.

Assignments (10)