IP Library › Granted Patent US 8,058,856
Granted Patent B2
US 8,058,856 · App. 12/153,126 · Granted Nov 15, 2011

Multi-phase DC-DC converter and method for balancing channel currents

Assignee: UPI Semiconductor Corporation
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Quick Facts
Patent No.
US 8,058,856
App. No.
12/153,126
Granted
Nov 15, 2011
Kind
B2
Abstract

A multi-phase DC-DC converter is provided. A plurality of switching sets are coupled to an output, wherein each switching set includes a phase node. A plurality of inductors are separately coupled between the phase nodes and the output. A sense circuit has a plurality of sense units separately coupled to the phase nodes, each sensing a signal from the corresponding phase node and generating a sensing signal. A PWM generator includes a plurality of subtracting units, each subtracting a first signal from one of the sensing signals to generate a difference signal, wherein the first signal is generated by summing each of the sensing signals divided by a predetermined value except for the one of the sensing signals. The PWM generator generates a plurality of PWM signals to balance the currents of the inductors according to the difference signals.

Claims (22)

1. A multi-phase DC-DC converter, comprising:

a plurality of switching sets for generating an output voltage at an output, wherein each switching set comprises a phase node;

a plurality of output inductors separately coupled between the phase nodes and the output;

a sense circuit having a plurality of sense units separately coupled to the phase nodes, each sense unit for sensing a signal from the corresponding phase node and generating a sensing signal according to the signal from the corresponding phase; and

a PWM generator for generating a plurality of PWM signals to balance a plurality of currents of the output inductors, comprising:

an error amplifier for comparing a reference voltage with the output voltage to generate an error signal;

a plurality of calculating circuits, each comprising:

a subtracting unit for subtracting a first signal from one of the sensing signals to generate a difference signal, wherein the first signal is generated by summing each of the sensing signals divided by a predetermined value except for the one of the sensing signals; and

a summing unit for summing the difference signal and a ramp signal to generate a second signal; and

a plurality of comparators separately coupled to the calculating circuits, each comparing the error signal with the corresponding second signal to generate the PWM signal,

wherein the switching sets generate the output voltage according to the PWM signals, and each of the difference signals is greater than 0.

2. The multi-phase DC-DC converter as claimed in claim 1 , wherein an amount of sensing signals is equal to N, and the predetermined value is equal to N−1.

3. The multi-phase DC-DC converter as claimed in claim 1 , wherein the calculating circuit further comprises a first multiplying unit for adjusting a gain of the one of the sensing signals, and a second multiplying unit for adjusting a gain of the first signal.

4. A method for balancing a plurality of channel currents in a multi-phase DC-DC converter, wherein the multi-phase DC-DC converter has an output voltage and a plurality of phase nodes, comprising:

sensing a plurality of signals from the corresponding phase nodes respectively, wherein each signal corresponds to the corresponding channel current;

generating a plurality of sensing signals according to the sensed signals, respectively;

comparing a reference voltage with the output voltage to generate an error signal;

subtracting a first signal from one of the sensing signals to generate a difference signal and summing the difference signal and a ramp signal to generate a second signal for each of the corresponding phase nodes, wherein the first signal is generated by summing each of the sensing signals divided by a predetermined value except for the one of the sensing signals;

comparing the error signal with the second signals to generate a plurality of PWM signals, respectively; and

adjusting the channel currents according to the PWM signals, respectively, wherein each of the difference signals is greater than 0.

5. The method as claimed in claim 4 , wherein an amount of sensing signals is equal to N, and the predetermined value is equal to N−1.

6. The method as claimed in claim 4 , wherein subtracting the first signal from the one of the sensing signals further comprises: adjusting a gain of the one of the sensing signals; and adjusting a gain of the first signal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 14, 2008
From: HUANG, HUA-CHIANG
To: UPI SEMICONDUCTOR CORPORATION
Reel/Frame 021017/0766 →
Continuity (2)
Provisional Application 60957952 · Aug 24, 2007
Related Publication 20090051335A1 · Feb 26, 2009