Semiconductor chip
In a chip, a transfer unit is provided between a physical layer processing unit and a link unit so that multiple lanes of data processed by the physical layer processing unit are transferred to the link unit. The transfer unit includes: multiple transfer unit input terminals inputting the multiple lanes of data processed by the physical layer processing unit; multiple transfer unit output terminals respectively connected to multiple input terminals of the link unit so as to output data input from one of the multiple transfer unit input terminals to each of the multiple input terminals of the link unit; and a switching unit switching the data, which is input from any one of the transfer unit input terminals, to be output from each of the transfer unit output terminals in response to a control signal from a control signal terminal.
1 . A semiconductor chip, comprising:
a first processing unit;
a second processing unit operating with a frequency lower than an operating frequency of the first processing unit;
a transfer unit provided between the first processing unit and the second processing unit and transferring a plurality of pieces of data between the first processing unit and the second processing unit; and
a control signal terminal inputting a control signal to the transfer unit,
wherein the transfer unit includes:
a plurality of transfer unit input terminals respectively inputting the plurality of pieces of data from a transmission-side processing unit which is a transmission side of one of the first processing unit and the second processing unit;
a plurality of transfer unit output terminals respectively corresponding to the plurality of transfer unit input terminals, respectively, and outputting the plurality of pieces of data input from the corresponding transfer unit input terminals to a reception-side processing unit which is a reception side of one of the first processing unit and the second processing unit; and
a switching unit switching a correspondence relation between the plurality of transfer unit input terminals and the plurality of transfer unit output terminals in response to the control signal from the control signal terminal.
2 . The semiconductor chip according to claim 1 , wherein the transfer unit further includes a timing correction unit correcting a transfer time according to the switching by the switching unit so that the transfer time for transferring data through transfer paths between the plurality of transfer unit input terminals and the plurality of transfer unit output terminals corresponding to the plurality of transfer unit input terminals is set to be constant with respect to the plurality of pieces of data.
3 . The semiconductor chip according to claim 2 , wherein:
the timing correction unit comprises a buffer provided to each of the transfer paths for the plurality of pieces of data; and
the number of buffers is increased as the transfer paths increase in length.
4 . The semiconductor chip according to claim 1 , wherein:
the semiconductor chip is compliant with Peripheral Component Interconnect (PCI) Express;
the plurality of pieces of data respectively correspond to a plurality of lanes;
the transmission-side processing unit comprises a physical layer processing unit performing physical layer processing;
the reception-side processing unit comprises a data link layer processing unit performing data link layer processing for the plurality of pieces of data obtained from the physical layer processing unit;
the transfer unit transfers the plurality of pieces of data obtained from the physical layer processing unit to the data link layer processing unit; and
each of the plurality of transfer unit input terminals and each of the plurality of transfer unit output terminals form a group of a plurality of terminals corresponding to one of the plurality of lanes.
5 . The semiconductor chip according to claim 2 , wherein:
the semiconductor chip is compliant with Peripheral Component Interconnect (PCI) Express;
the plurality of pieces of data respectively correspond to a plurality of lanes;
the transmission-side processing unit comprises a physical layer processing unit performing physical layer processing;
the reception-side processing unit comprises a data link layer processing unit performing data link layer processing for the plurality of pieces of data obtained from the physical layer processing unit;
the transfer unit transfers the plurality of pieces of data obtained from the physical layer processing unit to the data link layer processing unit; and
each of the plurality of transfer unit input terminals and each of the plurality of transfer unit output terminals form a group of a plurality of terminals corresponding to one of the plurality of lanes.
6 . The semiconductor chip according to claim 3 , wherein:
the semiconductor chip is compliant with Peripheral Component Interconnect (PCI) Express;
the plurality of pieces of data respectively correspond to a plurality of lanes;
the transmission-side processing unit comprises a physical layer processing unit performing physical layer processing;
the reception-side processing unit comprises a data link layer processing unit performing data link layer processing for the plurality of pieces of data obtained from the physical layer processing unit;
the transfer unit transfers the plurality of pieces of data obtained from the physical layer processing unit to the data link layer processing unit; and
each of the plurality of transfer unit input terminals and each of the plurality of transfer unit output terminals form a group of a plurality of terminals corresponding to one of the plurality of lanes.
7 . The semiconductor chip according to claim 1 , wherein:
the semiconductor chip is compliant with Peripheral Component Interconnect (PCI) Express;
the plurality of pieces of data respectively correspond to a plurality of lanes;
the transmission-side processing unit comprises a data link layer processing unit performing data link layer processing;
the reception-side processing unit comprises a physical layer processing unit performing physical layer processing for the plurality of pieces of data obtained from the physical layer processing unit;
the transfer unit transfers the plurality of pieces of data obtained from the data link layer processing unit to the physical layer processing unit; and
each of the plurality of transfer unit input terminals and each of the plurality of transfer unit output terminals form a group of a plurality of terminals corresponding to one of the plurality of lanes.
8 . The semiconductor chip according to claim 2 , wherein:
the semiconductor chip is compliant with Peripheral Component Interconnect (PCI) Express;
the plurality of pieces of data respectively correspond to a plurality of lanes;
the transmission-side processing unit comprises a data link layer processing unit performing data link layer processing;
the reception-side processing unit comprises a physical layer processing unit performing physical layer processing for the plurality of pieces of data obtained from the physical layer processing unit;
the transfer unit transfers the plurality of pieces of data obtained from the data link layer processing unit to the physical layer processing unit; and
each of the plurality of transfer unit input terminals and each of the plurality of transfer unit output terminals form a group of a plurality of terminals corresponding to one of the plurality of lanes.
9 . The semiconductor chip according to claim 3 , wherein:
the semiconductor chip is compliant with Peripheral Component Interconnect (PCI) Express;
the plurality of pieces of data respectively correspond to a plurality of lanes;
the transmission-side processing unit comprises a data link layer processing unit performing data link layer processing;
the reception-side processing unit comprises a physical layer processing unit performing physical layer processing for the plurality of pieces of data obtained from the physical layer processing unit;
the transfer unit transfers the plurality of pieces of data obtained from the data link layer processing unit to the physical layer processing unit; and
each of the plurality of transfer unit input terminals and each of the plurality of transfer unit output terminals form a group of a plurality of terminals corresponding to one of the plurality of lanes.
10 . A semiconductor chip, comprising:
a transfer unit; and
a control signal terminal inputting a control signal to the transfer unit,
wherein the transfer unit includes:
a plurality of transfer unit input terminals respectively inputting a plurality of pieces of data;
a plurality of transfer unit output terminals respectively corresponding to the plurality of transfer unit input terminals and outputting the plurality of pieces of data input from the corresponding transfer unit input terminals;
a switching unit switching a correspondence relation between the plurality of transfer unit input terminals and the plurality of transfer unit output terminals in response to the control signal from the control signal terminal; and
a timing correction unit correcting a transfer time according to the switching by the switching unit so that the transfer time for transferring data through transfer paths between the plurality of transfer unit input terminals and the plurality of transfer unit output terminals corresponding to the plurality of transfer unit input terminals is set to be constant with respect to the plurality of pieces of data.
11 . The semiconductor chip according to claim 10 , wherein:
the timing correction unit comprises a buffer provided to the transfer paths for each of the plurality of pieces of data; and
the number of buffers is increased as the transfer paths increase in length.
12 . The semiconductor chip according to claim 10 , further comprising a built-in processing circuit,
wherein the transfer unit is provided between the built-in processing circuit and an outside and transfers the plurality of pieces of data between the built-in processing circuit and the outside.
13 . The semiconductor chip according to claim 11 , further comprising a built-in processing circuit,
wherein the transfer unit is provided between the built-in processing circuit and an outside and transfers the plurality of pieces of data between the built-in processing circuit and the outside.
14 . The semiconductor chip according to claim 10 , wherein:
the built-in processing circuit includes:
a first processing unit; and
a second processing unit operating with a frequency lower than an operating frequency of the first processing unit; and
the transfer unit is provided between the first processing unit and the second processing unit and transfers the plurality of pieces of data from a transmission-side processing unit which is a transmission side of one of the first processing unit and the second processing unit, to a reception-side processing unit which is a reception side of one of the first processing unit and the second processing unit.
15 . The semiconductor chip according to claim 11 , wherein:
the built-in processing circuit includes:
a first processing unit; and
a second processing unit operating with a frequency lower than an operating frequency of the first processing unit; and
the transfer unit is provided between the first processing unit and the second processing unit and transfers the plurality of pieces of data from a transmission-side processing unit which is a transmission side of one of the first processing unit and the second processing unit, to a reception-side processing unit which is a reception side of one of the first processing unit and the second processing unit.
16 . The semiconductor chip according to claim 14 , wherein:
the semiconductor chip is compliant with Peripheral Component Interconnect (PCI) Express;
the plurality of pieces of data respectively correspond to a plurality of lanes;
the transmission-side processing unit comprises a physical layer processing unit performing physical layer processing;
the reception-side processing unit comprises a data link layer processing unit performing data link layer processing for the plurality of pieces of data obtained from the physical layer processing unit;
the transfer unit transfers the plurality of pieces of data obtained from the physical layer processing unit to the data link layer processing unit; and
each of the plurality of transfer unit input terminals and each of the plurality of transfer unit output terminals form a group of a plurality of terminals corresponding to one of the plurality of lanes.
17 . The semiconductor chip according to claim 15 , wherein:
the semiconductor chip is compliant with Peripheral Component Interconnect (PCI) Express;
the plurality of pieces of data respectively correspond to a plurality of lanes;
the transmission-side processing unit comprises a physical layer processing unit performing physical layer processing;
the reception-side processing unit comprises a data link layer processing unit performing data link layer processing for the plurality of pieces of data obtained from the physical layer processing unit;
the transfer unit transfers the plurality of pieces of data obtained from the physical layer processing unit to the data link layer processing unit; and
each of the plurality of transfer unit input terminals and each of the plurality of transfer unit output terminals form a group of a plurality of terminals corresponding to one of the plurality of lanes.
18 . The semiconductor chip according to claim 14 , wherein:
the semiconductor chip is compliant with Peripheral Component Interconnect (PCI) Express;
the plurality of pieces of data respectively correspond to a plurality of lanes;
the transmission-side processing unit comprises a data link layer processing unit performing data link layer processing;
the reception-side processing unit comprises a physical layer processing unit performing physical layer processing for the plurality of pieces of data obtained from the physical layer processing unit;
the transfer unit transfers the plurality of pieces of data obtained from the data link layer processing unit to the physical layer processing unit; and
each of the plurality of transfer unit input terminals and each of the plurality of transfer unit output terminals form a group of a plurality of terminals corresponding to one of the plurality of lanes.
19 . The semiconductor chip according to claim 15 , wherein:
the semiconductor chip is compliant with Peripheral Component Interconnect (PCI) Express;
the plurality of pieces of data respectively correspond to a plurality of lanes;
the transmission-side processing unit comprises a data link layer processing unit performing data link layer processing;
the reception-side processing unit comprises a physical layer processing unit performing physical layer processing for the plurality of pieces of data obtained from the physical layer processing unit;
the transfer unit transfers the plurality of pieces of data obtained from the data link layer processing unit to the physical layer processing unit; and
each of the plurality of transfer unit input terminals and each of the plurality of transfer unit output terminals form a group of a plurality of terminals corresponding to one of the plurality of lanes.