A/D converter preventing results of A/D conversion from being overwritten
View Patent ↗An A/D converter capable of generating an interrupt for requesting a control circuit to read the results of A/D conversion, in desired timing. Analog signals input from channels selected by a channel-selecting section are input to an A/D conversion section, and are sequentially A/D-converted. The results of A/D conversion are sequentially stored in different stages of a FIFO. A stage number-counting section counts the number of the stages of the FIFO where the results of A/D conversion are stored. An interrupt signal-delivering section outputs an interrupt signal for requesting a CPU to read the results of A/D conversion when the number of stages counted by the stage number-counting section is equal to an interrupt-generating stage number set by an interrupt-generating stage number-setting section.
1. An A/D converter for A/D-converting analog signals input from a plurality of channels, comprising:
a channel-selecting section selecting channels from said plurality of channels, for A/D conversion of the analog signals;
an A/D conversion section sequentially A/D-converting the analog signals from the selected channels on a channel-by-channel basis;
a FIFO including a plurality of stages of storage areas, and sequentially storing results of A/D conversion on a channel-by-channel basis in different ones of the plurality of stages;
a stage number-counting section counting a number of stages of said FIFO where the results of A/D conversion are stored;
an interrupt-generating stage number-setting section setting an interrupt-generating stage number; and
an interrupt signal-delivering section delivering an interrupt signal for requesting a control circuit reading the results of A/D conversion to read the results of A/D conversion, when the number of stages counted by said stage number-counting section becomes equal to the interrupt-generating stage number.
2. An A/D converter as claimed in claim 1 , further comprising:
a channel-setting section setting a channel group comprising a plurality of channels for A/D-conversion of the analog signals, and
a control section reading the channel group set by said channel-setting section, and supplying selection signals for causing said channel-selecting section to sequentially select the channels of the channel group.
3. An A/D converter as claimed in claim 2 , further comprising:
a repeat-setting section setting whether or not the A/D conversion is to be repeated,
wherein said control section reads the channel group set by said channel-setting section if repeat of the A/D conversion has been set by said repeat-setting section when the A/D conversion of the channel group is terminated, and supplies the selection signals for causing said channel-selecting section to sequentially select the channels of the read channel group, to said channel-selecting section.
4. An A/D converter as claimed in claim 2 , wherein
said control section reads the channel group set by said channel-setting section when the A/D conversion of the channel group by said A/D conversion section is terminated.
5. An A/D converter as claimed in claim 1 , wherein
the interrupt-generating stage number is set in desired timing by said interrupt-generating stage number-setting section.
6. An A/D converter as claimed in claim 2 , wherein
the channel group is set in desired timing by said channel-setting section.
7. An A/D converter as claimed in claim 3 , wherein
whether or not the A/D conversion is to be repeated is set in desired timing by said repeat-setting section.