Semiconductor device
View Patent ↗When a plurality of output buffer circuits are provided, chip layout size, power consumption, and number of pins of an LSI circuit are reduced. A voltage generation circuit generates reference voltages corresponding respectively to the output buffer circuits. A comparison circuit compares the reference voltages with an output voltage of a dummy buffer circuit. A counter counts a clock signal until a comparison result of the comparison circuit matches. The dummy buffer circuit adjusts output impedance corresponding respectively to the output buffer circuits based on a count value of the counter. Adjustment value holders hold respective count values when a comparison result of the comparison circuit, obtained based on respective corresponding reference voltages, matches. The output buffer circuits respectively adjust output impedances based on respectively held count values.
1. A semiconductor device comprising:
a voltage generation circuit which generates reference voltages;
a dummy buffer circuit;
a comparison circuit which compares the reference voltages and an output voltage of said dummy buffer circuit;
a counter which counts a clock signal until a comparison result of said comparison circuit is matched, wherein said dummy buffer circuit adjusts its own output impedance based on a count value of said counter;
n (n being an integer greater than or equal to 2) adjustment value holding circuits which hold count values when a comparison result of said comparison circuit is matched; and
n output buffer circuits which respectively adjust their own output impedances, based on count values respectively held by said adjustment value holding circuits; wherein
said voltage generation circuit generates the reference voltages respectively corresponding to said n output buffer circuits, said n adjustment value holding circuits hold respective count values when a comparison result, obtained based on respectively corresponding reference voltages, matches, and said dummy buffer circuit adjusts its own output impedance corresponding respectively to said n output buffer circuits.
2. The semiconductor device according to claim 1 , wherein
said output buffer circuits comprise:
m (m being an integer greater than or equal to 2) first output transistors which are connected in parallel and drive output pads; and
m second output transistors that are of a conductivity type opposite to said first output transistors, are connected in parallel, and drive said output pads;
each of said voltage generation circuit, said comparison circuit, said counter, said dummy buffer circuit, and said n adjustment value holding circuits are provided in groups of 2, corresponding to said first and said second output transistors; and
respective driving counts of said first and said second output transistors are determined according to count values respectively held by two of said adjustment value holding circuits.
3. The semiconductor device according to claim 2 , wherein
said dummy buffer circuit comprises:
a first dummy buffer circuit including m first dummy transistors, which are connected in parallel and drive a first pseudo-pad; and
a second dummy buffer circuit including m second dummy transistors that are of a conductivity type opposite to said first dummy transistors, are connected in parallel, and drive a second pseudo-pad; and
respective driving counts of said first and said second dummy transistors are determined according to count values respectively held by two of said counters.
4. The semiconductor device according to claim 3 , wherein
said output buffer circuit is an output buffer circuit with output offset transistor comprising:
first output offset transistors connected in parallel to said first output transistors and having a conductivity type the same as said first output transistors; and
second output offset transistors connected in parallel to said second output transistors and having a conductivity type the same as said second output transistors;
said dummy buffer circuit comprises:
first offset transistors having a conductivity type the same as said first dummy transistors; and
second offset transistors having a conductivity type the same as said second dummy transistors;
and in cases in which said dummy buffer circuit determines driving count of each of said first and said second output transistors of said output buffer circuit with output offset transistor, control is performed so that said first offset transistors are connected in parallel to said first dummy transistors, and said second offset transistors are connected in parallel to said second dummy transistors.
5. The semiconductor device according to claim 4 , wherein said first output offset transistors and said first offset transistors are the same size, and said second output offset transistors and said second offset transistors are the same size.
6. The semiconductor device according to claim 4 , wherein
said dummy buffer circuit comprises at least 2 of said first offset transistors, and an equal number of said second offset transistors to that of said first offset transistors; and
in cases in which said dummy buffer circuit determines driving count of each of said first and said second output transistors of said output buffer circuit with output offset transistor, control is performed so that at least 2 of said first offset transistors are selectively connected in parallel to said first dummy transistors, and at least 2 of said second offset transistors are selectively connected in parallel to said second dummy transistors.
7. The semiconductor device according to claim 6 , wherein ON-time impedance of said first output offset transistors and total ON-time impedance of said selected first offset transistors are the same, and ON-time impedance of said second output offset transistors and total ON-time impedance of said selected second offset transistors are the same.