Semiconductor memory device, method of writing data therein, and method of reading data therefrom

1. A semiconductor memory device, comprising:

a first field-effect transistor provided in a double well;

m (m is a natural number) first conductive plugs electrically connected to one of a source region and a drain region of the first field-effect transistor; and

n (n is a natural number) second conductive plugs electrically connected to other of the source region and the drain region of the first field-effect transistor,

wherein m is smaller than n.

2. A semiconductor memory device according to claim 1 , further comprising:

a second field-effect transistor;

a detection circuit for detecting a difference between an output of the first field-effect transistor and an output of the second field-effect transistor.

3. A semiconductor memory device according to claim 2 , wherein only the first field-effect transistor out of the first field-effect transistor and the second field-effect transistor is provided in the double well.

4. A semiconductor memory device according to claim 2 , wherein both of the first field-effect transistor and the second field-effect transistor are provided in the same double well.

5. A semiconductor memory device according to claim 2 , wherein both of the first field-effect transistor and the second field-effect transistor are provided in double wells different from each other.

6. A semiconductor memory device according to claim 2 , wherein a gate width and a gate length of the first field-effect transistor are equal to a gate width and a gate length of the second field-effect transistor, respectively.

7. A semiconductor memory device according to claim 2 , wherein the gate lengths of the first field-effect transistor and the second field-effect transistor are larger than a minimum gate length of field-effect transistors provided in the semiconductor memory device.

8. A method of reading data from the semiconductor memory device according to claim 2 , comprising:

detecting the difference between the output of the first field-effect transistor and the output of the second field-effect transistor.

9. A method of reading data according to claim 8 , wherein the detecting the difference includes detecting a difference between an output potential of the first field-effect transistor and an output potential of the second field-effect transistor.

10. A semiconductor memory device according to claim 1 , wherein the first conductive plugs and the second conductive plugs are electrically connected to the source region and the drain region, respectively, of the first field-effect transistor.

11. A semiconductor memory device according to claim 1 , wherein the first conductive plugs and the second conductive plugs are provided in the same layer.

12. A semiconductor memory device according to claim 1 , wherein each of the first conductive plugs and the second conductive plugs comprises a contact plug.

13. A semiconductor memory device according to claim 1 , wherein each of the first conductive plugs and the second conductive plugs comprises a via plug.

14. A method of writing data in the semiconductor memory device according to claim 1 , comprising:

passing current so that resistance of at least one of the first conductive plugs is increased, through the at least one of the first conductive plugs.

15. A method of writing data according to claim 14 , wherein the passing current includes passing current through the at least one of the first conductive plugs by applying forward bias voltage between one of the source region and the drain region of the second field-effect transistor and the well region.